1* CoreSight Components:
2
3CoreSight components are compliant with the ARM CoreSight architecture
4specification and can be connected in various topologies to suit a particular
5SoCs tracing needs. These trace components can generally be classified as
6sinks, links and sources. Trace data produced by one or more sources flows
7through the intermediate links connecting the source to the currently selected
8sink. Each CoreSight component device should use these properties to describe
9its hardware characteristcs.
10
11* Required properties for all components *except* non-configurable replicators
12  and non-configurable funnels:
13
14	* compatible: These have to be supplemented with "arm,primecell" as
15	  drivers are using the AMBA bus interface.  Possible values include:
16		- Embedded Trace Buffer (version 1.0):
17			"arm,coresight-etb10", "arm,primecell";
18
19		- Trace Port Interface Unit:
20			"arm,coresight-tpiu", "arm,primecell";
21
22		- Trace Memory Controller, used for Embedded Trace Buffer(ETB),
23		  Embedded Trace FIFO(ETF) and Embedded Trace Router(ETR)
24		  configuration.  The configuration mode (ETB, ETF, ETR) is
25		  discovered at boot time when the device is probed.
26			"arm,coresight-tmc", "arm,primecell";
27
28		- Trace Programmable Funnel:
29			"arm,coresight-dynamic-funnel", "arm,primecell";
30			"arm,coresight-funnel", "arm,primecell"; (OBSOLETE. For
31				backward compatibility and will be removed)
32
33		- Embedded Trace Macrocell (version 3.x) and
34					Program Flow Trace Macrocell:
35			"arm,coresight-etm3x", "arm,primecell";
36
37		- Embedded Trace Macrocell (version 4.x):
38			"arm,coresight-etm4x", "arm,primecell";
39
40		- Coresight programmable Replicator :
41			"arm,coresight-dynamic-replicator", "arm,primecell";
42
43		- System Trace Macrocell:
44			"arm,coresight-stm", "arm,primecell"; [1]
45		- Coresight Address Translation Unit (CATU)
46			"arm,coresight-catu", "arm,primecell";
47
48	* reg: physical base address and length of the register
49	  set(s) of the component.
50
51	* clocks: the clocks associated to this component.
52
53	* clock-names: the name of the clocks referenced by the code.
54	  Since we are using the AMBA framework, the name of the clock
55	  providing the interconnect should be "apb_pclk", and some
56	  coresight blocks also have an additional clock "atclk", which
57	  clocks the core of that coresight component. The latter clock
58	  is optional.
59
60	* port or ports: see "Graph bindings for Coresight" below.
61
62* Additional required property for Embedded Trace Macrocell (version 3.x and
63  version 4.x):
64	* cpu: the cpu phandle this ETM/PTM is affined to. Do not
65	  assume it to default to CPU0 if omitted.
66
67* Additional required properties for System Trace Macrocells (STM):
68	* reg: along with the physical base address and length of the register
69	  set as described above, another entry is required to describe the
70	  mapping of the extended stimulus port area.
71
72	* reg-names: the only acceptable values are "stm-base" and
73	  "stm-stimulus-base", each corresponding to the areas defined in "reg".
74
75* Required properties for devices that don't show up on the AMBA bus, such as
76  non-configurable replicators and non-configurable funnels:
77
78	* compatible: Currently supported value is (note the absence of the
79	  AMBA markee):
80		- Coresight Non-configurable Replicator:
81			"arm,coresight-static-replicator";
82			"arm,coresight-replicator"; (OBSOLETE. For backward
83				compatibility and will be removed)
84
85		- Coresight Non-configurable Funnel:
86			"arm,coresight-static-funnel";
87
88	* port or ports: see "Graph bindings for Coresight" below.
89
90* Optional properties for ETM/PTMs:
91
92	* arm,cp14: must be present if the system accesses ETM/PTM management
93	  registers via co-processor 14.
94
95* Optional property for TMC:
96
97	* arm,buffer-size: size of contiguous buffer space for TMC ETR
98	  (embedded trace router). This property is obsolete. The buffer size
99	  can be configured dynamically via buffer_size property in sysfs.
100
101	* arm,scatter-gather: boolean. Indicates that the TMC-ETR can safely
102	  use the SG mode on this system.
103
104* Optional property for CATU :
105	* interrupts : Exactly one SPI may be listed for reporting the address
106	  error
107
108Graph bindings for Coresight
109-------------------------------
110
111Coresight components are interconnected to create a data path for the flow of
112trace data generated from the "sources" to their collection points "sink".
113Each coresight component must describe the "input" and "output" connections.
114The connections must be described via generic DT graph bindings as described
115by the "bindings/graph.txt", where each "port" along with an "endpoint"
116component represents a hardware port and the connection.
117
118 * All output ports must be listed inside a child node named "out-ports"
119 * All input ports must be listed inside a child node named "in-ports".
120 * Port address must match the hardware port number.
121
122Example:
123
1241. Sinks
125	etb@20010000 {
126		compatible = "arm,coresight-etb10", "arm,primecell";
127		reg = <0 0x20010000 0 0x1000>;
128
129		clocks = <&oscclk6a>;
130		clock-names = "apb_pclk";
131		in-ports {
132			port {
133				etb_in_port: endpoint@0 {
134					remote-endpoint = <&replicator_out_port0>;
135				};
136			};
137		};
138	};
139
140	tpiu@20030000 {
141		compatible = "arm,coresight-tpiu", "arm,primecell";
142		reg = <0 0x20030000 0 0x1000>;
143
144		clocks = <&oscclk6a>;
145		clock-names = "apb_pclk";
146		in-ports {
147			port {
148				tpiu_in_port: endpoint@0 {
149					remote-endpoint = <&replicator_out_port1>;
150				};
151			};
152		};
153	};
154
155	etr@20070000 {
156		compatible = "arm,coresight-tmc", "arm,primecell";
157		reg = <0 0x20070000 0 0x1000>;
158
159		clocks = <&oscclk6a>;
160		clock-names = "apb_pclk";
161		in-ports {
162			port {
163				etr_in_port: endpoint {
164					remote-endpoint = <&replicator2_out_port0>;
165				};
166			};
167		};
168
169		out-ports {
170			port {
171				etr_out_port: endpoint {
172					remote-endpoint = <&catu_in_port>;
173				};
174			};
175		};
176	};
177
1782. Links
179	replicator {
180		/* non-configurable replicators don't show up on the
181		 * AMBA bus.  As such no need to add "arm,primecell".
182		 */
183		compatible = "arm,coresight-static-replicator";
184
185		out-ports {
186			#address-cells = <1>;
187			#size-cells = <0>;
188
189			/* replicator output ports */
190			port@0 {
191				reg = <0>;
192				replicator_out_port0: endpoint {
193					remote-endpoint = <&etb_in_port>;
194				};
195			};
196
197			port@1 {
198				reg = <1>;
199				replicator_out_port1: endpoint {
200					remote-endpoint = <&tpiu_in_port>;
201				};
202			};
203		};
204
205		in-ports {
206			port {
207				replicator_in_port0: endpoint {
208					remote-endpoint = <&funnel_out_port0>;
209				};
210			};
211		};
212	};
213
214	funnel {
215		/*
216		 * non-configurable funnel don't show up on the AMBA
217		 * bus.  As such no need to add "arm,primecell".
218		 */
219		compatible = "arm,coresight-static-funnel";
220		clocks = <&crg_ctrl HI3660_PCLK>;
221		clock-names = "apb_pclk";
222
223		out-ports {
224			port {
225				combo_funnel_out: endpoint {
226					remote-endpoint = <&top_funnel_in>;
227				};
228			};
229		};
230
231		in-ports {
232			#address-cells = <1>;
233			#size-cells = <0>;
234
235			port@0 {
236				reg = <0>;
237				combo_funnel_in0: endpoint {
238					remote-endpoint = <&cluster0_etf_out>;
239				};
240			};
241
242			port@1 {
243				reg = <1>;
244				combo_funnel_in1: endpoint {
245					remote-endpoint = <&cluster1_etf_out>;
246				};
247			};
248		};
249	};
250
251	funnel@20040000 {
252		compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
253		reg = <0 0x20040000 0 0x1000>;
254
255		clocks = <&oscclk6a>;
256		clock-names = "apb_pclk";
257		out-ports {
258			port {
259				funnel_out_port0: endpoint {
260					remote-endpoint =
261							<&replicator_in_port0>;
262				};
263			};
264		};
265
266		in-ports {
267			#address-cells = <1>;
268			#size-cells = <0>;
269
270			port@0 {
271				reg = <0>;
272				funnel_in_port0: endpoint {
273					remote-endpoint = <&ptm0_out_port>;
274				};
275			};
276
277			port@1 {
278				reg = <1>;
279				funnel_in_port1: endpoint {
280					remote-endpoint = <&ptm1_out_port>;
281				};
282			};
283
284			port@2 {
285				reg = <2>;
286				funnel_in_port2: endpoint {
287					remote-endpoint = <&etm0_out_port>;
288				};
289			};
290
291		};
292	};
293
2943. Sources
295	ptm@2201c000 {
296		compatible = "arm,coresight-etm3x", "arm,primecell";
297		reg = <0 0x2201c000 0 0x1000>;
298
299		cpu = <&cpu0>;
300		clocks = <&oscclk6a>;
301		clock-names = "apb_pclk";
302		out-ports {
303			port {
304				ptm0_out_port: endpoint {
305					remote-endpoint = <&funnel_in_port0>;
306				};
307			};
308		};
309	};
310
311	ptm@2201d000 {
312		compatible = "arm,coresight-etm3x", "arm,primecell";
313		reg = <0 0x2201d000 0 0x1000>;
314
315		cpu = <&cpu1>;
316		clocks = <&oscclk6a>;
317		clock-names = "apb_pclk";
318		out-ports {
319			port {
320				ptm1_out_port: endpoint {
321					remote-endpoint = <&funnel_in_port1>;
322				};
323			};
324		};
325	};
326
3274. STM
328	stm@20100000 {
329		compatible = "arm,coresight-stm", "arm,primecell";
330		reg = <0 0x20100000 0 0x1000>,
331		      <0 0x28000000 0 0x180000>;
332		reg-names = "stm-base", "stm-stimulus-base";
333
334		clocks = <&soc_smc50mhz>;
335		clock-names = "apb_pclk";
336		out-ports {
337			port {
338				stm_out_port: endpoint {
339					remote-endpoint = <&main_funnel_in_port2>;
340				};
341			};
342		};
343	};
344
3455. CATU
346
347	catu@207e0000 {
348		compatible = "arm,coresight-catu", "arm,primecell";
349		reg = <0 0x207e0000 0 0x1000>;
350
351		clocks = <&oscclk6a>;
352		clock-names = "apb_pclk";
353
354		interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
355		in-ports {
356			port {
357				catu_in_port: endpoint {
358					remote-endpoint = <&etr_out_port>;
359				};
360			};
361		};
362	};
363
364[1]. There is currently two version of STM: STM32 and STM500.  Both
365have the same HW interface and as such don't need an explicit binding name.
366