1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Synopsys DesignWare 8250 driver.
4 *
5 * Copyright 2011 Picochip, Jamie Iles.
6 * Copyright 2013 Intel Corporation
7 *
8 * The Synopsys DesignWare 8250 has an extra feature whereby it detects if the
9 * LCR is written whilst busy. If it is, then a busy detect interrupt is
10 * raised, the LCR needs to be rewritten and the uart status register read.
11 */
12 #include <linux/acpi.h>
13 #include <linux/clk.h>
14 #include <linux/delay.h>
15 #include <linux/device.h>
16 #include <linux/io.h>
17 #include <linux/mod_devicetable.h>
18 #include <linux/module.h>
19 #include <linux/notifier.h>
20 #include <linux/of.h>
21 #include <linux/platform_device.h>
22 #include <linux/pm_runtime.h>
23 #include <linux/property.h>
24 #include <linux/reset.h>
25 #include <linux/slab.h>
26 #include <linux/workqueue.h>
27
28 #include <asm/byteorder.h>
29
30 #include <linux/serial_8250.h>
31 #include <linux/serial_reg.h>
32
33 #include "8250_dwlib.h"
34
35 /* Offsets for the DesignWare specific registers */
36 #define DW_UART_USR 0x1f /* UART Status Register */
37 #define DW_UART_DMASA 0xa8 /* DMA Software Ack */
38
39 #define OCTEON_UART_USR 0x27 /* UART Status Register */
40
41 #define RZN1_UART_TDMACR 0x10c /* DMA Control Register Transmit Mode */
42 #define RZN1_UART_RDMACR 0x110 /* DMA Control Register Receive Mode */
43
44 /* DesignWare specific register fields */
45 #define DW_UART_MCR_SIRE BIT(6)
46
47 /* Renesas specific register fields */
48 #define RZN1_UART_xDMACR_DMA_EN BIT(0)
49 #define RZN1_UART_xDMACR_1_WORD_BURST (0 << 1)
50 #define RZN1_UART_xDMACR_4_WORD_BURST (1 << 1)
51 #define RZN1_UART_xDMACR_8_WORD_BURST (2 << 1)
52 #define RZN1_UART_xDMACR_BLK_SZ(x) ((x) << 3)
53
54 /* Quirks */
55 #define DW_UART_QUIRK_OCTEON BIT(0)
56 #define DW_UART_QUIRK_ARMADA_38X BIT(1)
57 #define DW_UART_QUIRK_SKIP_SET_RATE BIT(2)
58 #define DW_UART_QUIRK_IS_DMA_FC BIT(3)
59
clk_to_dw8250_data(struct notifier_block * nb)60 static inline struct dw8250_data *clk_to_dw8250_data(struct notifier_block *nb)
61 {
62 return container_of(nb, struct dw8250_data, clk_notifier);
63 }
64
work_to_dw8250_data(struct work_struct * work)65 static inline struct dw8250_data *work_to_dw8250_data(struct work_struct *work)
66 {
67 return container_of(work, struct dw8250_data, clk_work);
68 }
69
dw8250_modify_msr(struct uart_port * p,int offset,int value)70 static inline int dw8250_modify_msr(struct uart_port *p, int offset, int value)
71 {
72 struct dw8250_data *d = to_dw8250_data(p->private_data);
73
74 /* Override any modem control signals if needed */
75 if (offset == UART_MSR) {
76 value |= d->msr_mask_on;
77 value &= ~d->msr_mask_off;
78 }
79
80 return value;
81 }
82
dw8250_force_idle(struct uart_port * p)83 static void dw8250_force_idle(struct uart_port *p)
84 {
85 struct uart_8250_port *up = up_to_u8250p(p);
86 unsigned int lsr;
87
88 serial8250_clear_and_reinit_fifos(up);
89
90 /*
91 * With PSLVERR_RESP_EN parameter set to 1, the device generates an
92 * error response when an attempt to read an empty RBR with FIFO
93 * enabled.
94 */
95 if (up->fcr & UART_FCR_ENABLE_FIFO) {
96 lsr = p->serial_in(p, UART_LSR);
97 if (!(lsr & UART_LSR_DR))
98 return;
99 }
100
101 (void)p->serial_in(p, UART_RX);
102 }
103
dw8250_check_lcr(struct uart_port * p,int value)104 static void dw8250_check_lcr(struct uart_port *p, int value)
105 {
106 void __iomem *offset = p->membase + (UART_LCR << p->regshift);
107 int tries = 1000;
108
109 /* Make sure LCR write wasn't ignored */
110 while (tries--) {
111 unsigned int lcr = p->serial_in(p, UART_LCR);
112
113 if ((value & ~UART_LCR_SPAR) == (lcr & ~UART_LCR_SPAR))
114 return;
115
116 dw8250_force_idle(p);
117
118 #ifdef CONFIG_64BIT
119 if (p->type == PORT_OCTEON)
120 __raw_writeq(value & 0xff, offset);
121 else
122 #endif
123 if (p->iotype == UPIO_MEM32)
124 writel(value, offset);
125 else if (p->iotype == UPIO_MEM32BE)
126 iowrite32be(value, offset);
127 else
128 writeb(value, offset);
129 }
130 /*
131 * FIXME: this deadlocks if port->lock is already held
132 * dev_err(p->dev, "Couldn't set LCR to %d\n", value);
133 */
134 }
135
136 /* Returns once the transmitter is empty or we run out of retries */
dw8250_tx_wait_empty(struct uart_port * p)137 static void dw8250_tx_wait_empty(struct uart_port *p)
138 {
139 struct uart_8250_port *up = up_to_u8250p(p);
140 unsigned int tries = 20000;
141 unsigned int delay_threshold = tries - 1000;
142 unsigned int lsr;
143
144 while (tries--) {
145 lsr = readb (p->membase + (UART_LSR << p->regshift));
146 up->lsr_saved_flags |= lsr & up->lsr_save_mask;
147
148 if (lsr & UART_LSR_TEMT)
149 break;
150
151 /* The device is first given a chance to empty without delay,
152 * to avoid slowdowns at high bitrates. If after 1000 tries
153 * the buffer has still not emptied, allow more time for low-
154 * speed links. */
155 if (tries < delay_threshold)
156 udelay (1);
157 }
158 }
159
dw8250_serial_out(struct uart_port * p,int offset,int value)160 static void dw8250_serial_out(struct uart_port *p, int offset, int value)
161 {
162 struct dw8250_data *d = to_dw8250_data(p->private_data);
163
164 writeb(value, p->membase + (offset << p->regshift));
165
166 if (offset == UART_LCR && !d->uart_16550_compatible)
167 dw8250_check_lcr(p, value);
168 }
169
dw8250_serial_out38x(struct uart_port * p,int offset,int value)170 static void dw8250_serial_out38x(struct uart_port *p, int offset, int value)
171 {
172 /* Allow the TX to drain before we reconfigure */
173 if (offset == UART_LCR)
174 dw8250_tx_wait_empty(p);
175
176 dw8250_serial_out(p, offset, value);
177 }
178
dw8250_serial_in(struct uart_port * p,int offset)179 static unsigned int dw8250_serial_in(struct uart_port *p, int offset)
180 {
181 unsigned int value = readb(p->membase + (offset << p->regshift));
182
183 return dw8250_modify_msr(p, offset, value);
184 }
185
186 #ifdef CONFIG_64BIT
dw8250_serial_inq(struct uart_port * p,int offset)187 static unsigned int dw8250_serial_inq(struct uart_port *p, int offset)
188 {
189 unsigned int value;
190
191 value = (u8)__raw_readq(p->membase + (offset << p->regshift));
192
193 return dw8250_modify_msr(p, offset, value);
194 }
195
dw8250_serial_outq(struct uart_port * p,int offset,int value)196 static void dw8250_serial_outq(struct uart_port *p, int offset, int value)
197 {
198 struct dw8250_data *d = to_dw8250_data(p->private_data);
199
200 value &= 0xff;
201 __raw_writeq(value, p->membase + (offset << p->regshift));
202 /* Read back to ensure register write ordering. */
203 __raw_readq(p->membase + (UART_LCR << p->regshift));
204
205 if (offset == UART_LCR && !d->uart_16550_compatible)
206 dw8250_check_lcr(p, value);
207 }
208 #endif /* CONFIG_64BIT */
209
dw8250_serial_out32(struct uart_port * p,int offset,int value)210 static void dw8250_serial_out32(struct uart_port *p, int offset, int value)
211 {
212 struct dw8250_data *d = to_dw8250_data(p->private_data);
213
214 writel(value, p->membase + (offset << p->regshift));
215
216 if (offset == UART_LCR && !d->uart_16550_compatible)
217 dw8250_check_lcr(p, value);
218 }
219
dw8250_serial_in32(struct uart_port * p,int offset)220 static unsigned int dw8250_serial_in32(struct uart_port *p, int offset)
221 {
222 unsigned int value = readl(p->membase + (offset << p->regshift));
223
224 return dw8250_modify_msr(p, offset, value);
225 }
226
dw8250_serial_out32be(struct uart_port * p,int offset,int value)227 static void dw8250_serial_out32be(struct uart_port *p, int offset, int value)
228 {
229 struct dw8250_data *d = to_dw8250_data(p->private_data);
230
231 iowrite32be(value, p->membase + (offset << p->regshift));
232
233 if (offset == UART_LCR && !d->uart_16550_compatible)
234 dw8250_check_lcr(p, value);
235 }
236
dw8250_serial_in32be(struct uart_port * p,int offset)237 static unsigned int dw8250_serial_in32be(struct uart_port *p, int offset)
238 {
239 unsigned int value = ioread32be(p->membase + (offset << p->regshift));
240
241 return dw8250_modify_msr(p, offset, value);
242 }
243
244
dw8250_handle_irq(struct uart_port * p)245 static int dw8250_handle_irq(struct uart_port *p)
246 {
247 struct uart_8250_port *up = up_to_u8250p(p);
248 struct dw8250_data *d = to_dw8250_data(p->private_data);
249 unsigned int iir = p->serial_in(p, UART_IIR);
250 bool rx_timeout = (iir & 0x3f) == UART_IIR_RX_TIMEOUT;
251 unsigned int quirks = d->pdata->quirks;
252 unsigned int status;
253 unsigned long flags;
254
255 /*
256 * There are ways to get Designware-based UARTs into a state where
257 * they are asserting UART_IIR_RX_TIMEOUT but there is no actual
258 * data available. If we see such a case then we'll do a bogus
259 * read. If we don't do this then the "RX TIMEOUT" interrupt will
260 * fire forever.
261 *
262 * This problem has only been observed so far when not in DMA mode
263 * so we limit the workaround only to non-DMA mode.
264 */
265 if (!up->dma && rx_timeout) {
266 spin_lock_irqsave(&p->lock, flags);
267 status = serial_lsr_in(up);
268
269 if (!(status & (UART_LSR_DR | UART_LSR_BI)))
270 (void) p->serial_in(p, UART_RX);
271
272 spin_unlock_irqrestore(&p->lock, flags);
273 }
274
275 /* Manually stop the Rx DMA transfer when acting as flow controller */
276 if (quirks & DW_UART_QUIRK_IS_DMA_FC && up->dma && up->dma->rx_running && rx_timeout) {
277 spin_lock_irqsave(&p->lock, flags);
278 status = serial_lsr_in(up);
279 spin_unlock_irqrestore(&p->lock, flags);
280
281 if (status & (UART_LSR_DR | UART_LSR_BI)) {
282 dw8250_writel_ext(p, RZN1_UART_RDMACR, 0);
283 dw8250_writel_ext(p, DW_UART_DMASA, 1);
284 }
285 }
286
287 if (serial8250_handle_irq(p, iir))
288 return 1;
289
290 if ((iir & UART_IIR_BUSY) == UART_IIR_BUSY) {
291 /* Clear the USR */
292 (void)p->serial_in(p, d->pdata->usr_reg);
293
294 return 1;
295 }
296
297 return 0;
298 }
299
dw8250_clk_work_cb(struct work_struct * work)300 static void dw8250_clk_work_cb(struct work_struct *work)
301 {
302 struct dw8250_data *d = work_to_dw8250_data(work);
303 struct uart_8250_port *up;
304 unsigned long rate;
305
306 rate = clk_get_rate(d->clk);
307 if (rate <= 0)
308 return;
309
310 up = serial8250_get_port(d->data.line);
311
312 serial8250_update_uartclk(&up->port, rate);
313 }
314
dw8250_clk_notifier_cb(struct notifier_block * nb,unsigned long event,void * data)315 static int dw8250_clk_notifier_cb(struct notifier_block *nb,
316 unsigned long event, void *data)
317 {
318 struct dw8250_data *d = clk_to_dw8250_data(nb);
319
320 /*
321 * We have no choice but to defer the uartclk update due to two
322 * deadlocks. First one is caused by a recursive mutex lock which
323 * happens when clk_set_rate() is called from dw8250_set_termios().
324 * Second deadlock is more tricky and is caused by an inverted order of
325 * the clk and tty-port mutexes lock. It happens if clock rate change
326 * is requested asynchronously while set_termios() is executed between
327 * tty-port mutex lock and clk_set_rate() function invocation and
328 * vise-versa. Anyway if we didn't have the reference clock alteration
329 * in the dw8250_set_termios() method we wouldn't have needed this
330 * deferred event handling complication.
331 */
332 if (event == POST_RATE_CHANGE) {
333 queue_work(system_unbound_wq, &d->clk_work);
334 return NOTIFY_OK;
335 }
336
337 return NOTIFY_DONE;
338 }
339
340 static void
dw8250_do_pm(struct uart_port * port,unsigned int state,unsigned int old)341 dw8250_do_pm(struct uart_port *port, unsigned int state, unsigned int old)
342 {
343 if (!state)
344 pm_runtime_get_sync(port->dev);
345
346 serial8250_do_pm(port, state, old);
347
348 if (state)
349 pm_runtime_put_sync_suspend(port->dev);
350 }
351
dw8250_set_termios(struct uart_port * p,struct ktermios * termios,const struct ktermios * old)352 static void dw8250_set_termios(struct uart_port *p, struct ktermios *termios,
353 const struct ktermios *old)
354 {
355 unsigned long newrate = tty_termios_baud_rate(termios) * 16;
356 struct dw8250_data *d = to_dw8250_data(p->private_data);
357 long rate;
358 int ret;
359
360 clk_disable_unprepare(d->clk);
361 rate = clk_round_rate(d->clk, newrate);
362 if (rate > 0) {
363 /*
364 * Note that any clock-notifer worker will block in
365 * serial8250_update_uartclk() until we are done.
366 */
367 ret = clk_set_rate(d->clk, newrate);
368 if (!ret)
369 p->uartclk = rate;
370 }
371 clk_prepare_enable(d->clk);
372
373 dw8250_do_set_termios(p, termios, old);
374 }
375
dw8250_set_ldisc(struct uart_port * p,struct ktermios * termios)376 static void dw8250_set_ldisc(struct uart_port *p, struct ktermios *termios)
377 {
378 struct uart_8250_port *up = up_to_u8250p(p);
379 unsigned int mcr = p->serial_in(p, UART_MCR);
380
381 if (up->capabilities & UART_CAP_IRDA) {
382 if (termios->c_line == N_IRDA)
383 mcr |= DW_UART_MCR_SIRE;
384 else
385 mcr &= ~DW_UART_MCR_SIRE;
386
387 p->serial_out(p, UART_MCR, mcr);
388 }
389 serial8250_do_set_ldisc(p, termios);
390 }
391
392 /*
393 * dw8250_fallback_dma_filter will prevent the UART from getting just any free
394 * channel on platforms that have DMA engines, but don't have any channels
395 * assigned to the UART.
396 *
397 * REVISIT: This is a work around for limitation in the DMA Engine API. Once the
398 * core problem is fixed, this function is no longer needed.
399 */
dw8250_fallback_dma_filter(struct dma_chan * chan,void * param)400 static bool dw8250_fallback_dma_filter(struct dma_chan *chan, void *param)
401 {
402 return false;
403 }
404
dw8250_idma_filter(struct dma_chan * chan,void * param)405 static bool dw8250_idma_filter(struct dma_chan *chan, void *param)
406 {
407 return param == chan->device->dev;
408 }
409
dw8250_rzn1_get_dmacr_burst(int max_burst)410 static u32 dw8250_rzn1_get_dmacr_burst(int max_burst)
411 {
412 if (max_burst >= 8)
413 return RZN1_UART_xDMACR_8_WORD_BURST;
414 else if (max_burst >= 4)
415 return RZN1_UART_xDMACR_4_WORD_BURST;
416 else
417 return RZN1_UART_xDMACR_1_WORD_BURST;
418 }
419
dw8250_prepare_tx_dma(struct uart_8250_port * p)420 static void dw8250_prepare_tx_dma(struct uart_8250_port *p)
421 {
422 struct uart_port *up = &p->port;
423 struct uart_8250_dma *dma = p->dma;
424 u32 val;
425
426 dw8250_writel_ext(up, RZN1_UART_TDMACR, 0);
427 val = dw8250_rzn1_get_dmacr_burst(dma->txconf.dst_maxburst) |
428 RZN1_UART_xDMACR_BLK_SZ(dma->tx_size) |
429 RZN1_UART_xDMACR_DMA_EN;
430 dw8250_writel_ext(up, RZN1_UART_TDMACR, val);
431 }
432
dw8250_prepare_rx_dma(struct uart_8250_port * p)433 static void dw8250_prepare_rx_dma(struct uart_8250_port *p)
434 {
435 struct uart_port *up = &p->port;
436 struct uart_8250_dma *dma = p->dma;
437 u32 val;
438
439 dw8250_writel_ext(up, RZN1_UART_RDMACR, 0);
440 val = dw8250_rzn1_get_dmacr_burst(dma->rxconf.src_maxburst) |
441 RZN1_UART_xDMACR_BLK_SZ(dma->rx_size) |
442 RZN1_UART_xDMACR_DMA_EN;
443 dw8250_writel_ext(up, RZN1_UART_RDMACR, val);
444 }
445
dw8250_quirks(struct uart_port * p,struct dw8250_data * data)446 static void dw8250_quirks(struct uart_port *p, struct dw8250_data *data)
447 {
448 struct device_node *np = p->dev->of_node;
449
450 if (np) {
451 unsigned int quirks = data->pdata->quirks;
452 int id;
453
454 /* get index of serial line, if found in DT aliases */
455 id = of_alias_get_id(np, "serial");
456 if (id >= 0)
457 p->line = id;
458 #ifdef CONFIG_64BIT
459 if (quirks & DW_UART_QUIRK_OCTEON) {
460 p->serial_in = dw8250_serial_inq;
461 p->serial_out = dw8250_serial_outq;
462 p->flags = UPF_SKIP_TEST | UPF_SHARE_IRQ | UPF_FIXED_TYPE;
463 p->type = PORT_OCTEON;
464 data->skip_autocfg = true;
465 }
466 #endif
467
468 if (of_device_is_big_endian(np)) {
469 p->iotype = UPIO_MEM32BE;
470 p->serial_in = dw8250_serial_in32be;
471 p->serial_out = dw8250_serial_out32be;
472 }
473
474 if (quirks & DW_UART_QUIRK_ARMADA_38X)
475 p->serial_out = dw8250_serial_out38x;
476 if (quirks & DW_UART_QUIRK_SKIP_SET_RATE)
477 p->set_termios = dw8250_do_set_termios;
478 if (quirks & DW_UART_QUIRK_IS_DMA_FC) {
479 data->data.dma.txconf.device_fc = 1;
480 data->data.dma.rxconf.device_fc = 1;
481 data->data.dma.prepare_tx_dma = dw8250_prepare_tx_dma;
482 data->data.dma.prepare_rx_dma = dw8250_prepare_rx_dma;
483 }
484
485 } else if (acpi_dev_present("APMC0D08", NULL, -1)) {
486 p->iotype = UPIO_MEM32;
487 p->regshift = 2;
488 p->serial_in = dw8250_serial_in32;
489 data->uart_16550_compatible = true;
490 }
491
492 /* Platforms with iDMA 64-bit */
493 if (platform_get_resource_byname(to_platform_device(p->dev),
494 IORESOURCE_MEM, "lpss_priv")) {
495 data->data.dma.rx_param = p->dev->parent;
496 data->data.dma.tx_param = p->dev->parent;
497 data->data.dma.fn = dw8250_idma_filter;
498 }
499 }
500
dw8250_clk_disable_unprepare(void * data)501 static void dw8250_clk_disable_unprepare(void *data)
502 {
503 clk_disable_unprepare(data);
504 }
505
dw8250_reset_control_assert(void * data)506 static void dw8250_reset_control_assert(void *data)
507 {
508 reset_control_assert(data);
509 }
510
dw8250_probe(struct platform_device * pdev)511 static int dw8250_probe(struct platform_device *pdev)
512 {
513 struct uart_8250_port uart = {}, *up = &uart;
514 struct uart_port *p = &up->port;
515 struct device *dev = &pdev->dev;
516 struct dw8250_data *data;
517 struct resource *regs;
518 int irq;
519 int err;
520 u32 val;
521
522 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
523 if (!regs)
524 return dev_err_probe(dev, -EINVAL, "no registers defined\n");
525
526 irq = platform_get_irq_optional(pdev, 0);
527 /* no interrupt -> fall back to polling */
528 if (irq == -ENXIO)
529 irq = 0;
530 if (irq < 0)
531 return irq;
532
533 spin_lock_init(&p->lock);
534 p->mapbase = regs->start;
535 p->irq = irq;
536 p->handle_irq = dw8250_handle_irq;
537 p->pm = dw8250_do_pm;
538 p->type = PORT_8250;
539 p->flags = UPF_SHARE_IRQ | UPF_FIXED_PORT;
540 p->dev = dev;
541 p->iotype = UPIO_MEM;
542 p->serial_in = dw8250_serial_in;
543 p->serial_out = dw8250_serial_out;
544 p->set_ldisc = dw8250_set_ldisc;
545 p->set_termios = dw8250_set_termios;
546
547 p->membase = devm_ioremap(dev, regs->start, resource_size(regs));
548 if (!p->membase)
549 return -ENOMEM;
550
551 data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
552 if (!data)
553 return -ENOMEM;
554
555 data->data.dma.fn = dw8250_fallback_dma_filter;
556 data->pdata = device_get_match_data(p->dev);
557 p->private_data = &data->data;
558
559 data->uart_16550_compatible = device_property_read_bool(dev,
560 "snps,uart-16550-compatible");
561
562 err = device_property_read_u32(dev, "reg-shift", &val);
563 if (!err)
564 p->regshift = val;
565
566 err = device_property_read_u32(dev, "reg-io-width", &val);
567 if (!err && val == 4) {
568 p->iotype = UPIO_MEM32;
569 p->serial_in = dw8250_serial_in32;
570 p->serial_out = dw8250_serial_out32;
571 }
572
573 if (device_property_read_bool(dev, "dcd-override")) {
574 /* Always report DCD as active */
575 data->msr_mask_on |= UART_MSR_DCD;
576 data->msr_mask_off |= UART_MSR_DDCD;
577 }
578
579 if (device_property_read_bool(dev, "dsr-override")) {
580 /* Always report DSR as active */
581 data->msr_mask_on |= UART_MSR_DSR;
582 data->msr_mask_off |= UART_MSR_DDSR;
583 }
584
585 if (device_property_read_bool(dev, "cts-override")) {
586 /* Always report CTS as active */
587 data->msr_mask_on |= UART_MSR_CTS;
588 data->msr_mask_off |= UART_MSR_DCTS;
589 }
590
591 if (device_property_read_bool(dev, "ri-override")) {
592 /* Always report Ring indicator as inactive */
593 data->msr_mask_off |= UART_MSR_RI;
594 data->msr_mask_off |= UART_MSR_TERI;
595 }
596
597 /* Always ask for fixed clock rate from a property. */
598 device_property_read_u32(dev, "clock-frequency", &p->uartclk);
599
600 /* If there is separate baudclk, get the rate from it. */
601 data->clk = devm_clk_get_optional(dev, "baudclk");
602 if (data->clk == NULL)
603 data->clk = devm_clk_get_optional(dev, NULL);
604 if (IS_ERR(data->clk))
605 return PTR_ERR(data->clk);
606
607 INIT_WORK(&data->clk_work, dw8250_clk_work_cb);
608 data->clk_notifier.notifier_call = dw8250_clk_notifier_cb;
609
610 err = clk_prepare_enable(data->clk);
611 if (err)
612 return dev_err_probe(dev, err, "could not enable optional baudclk\n");
613
614 err = devm_add_action_or_reset(dev, dw8250_clk_disable_unprepare, data->clk);
615 if (err)
616 return err;
617
618 if (data->clk)
619 p->uartclk = clk_get_rate(data->clk);
620
621 /* If no clock rate is defined, fail. */
622 if (!p->uartclk)
623 return dev_err_probe(dev, -EINVAL, "clock rate not defined\n");
624
625 data->pclk = devm_clk_get_optional(dev, "apb_pclk");
626 if (IS_ERR(data->pclk))
627 return PTR_ERR(data->pclk);
628
629 err = clk_prepare_enable(data->pclk);
630 if (err)
631 return dev_err_probe(dev, err, "could not enable apb_pclk\n");
632
633 err = devm_add_action_or_reset(dev, dw8250_clk_disable_unprepare, data->pclk);
634 if (err)
635 return err;
636
637 data->rst = devm_reset_control_get_optional_exclusive(dev, NULL);
638 if (IS_ERR(data->rst))
639 return PTR_ERR(data->rst);
640
641 reset_control_deassert(data->rst);
642
643 err = devm_add_action_or_reset(dev, dw8250_reset_control_assert, data->rst);
644 if (err)
645 return err;
646
647 dw8250_quirks(p, data);
648
649 /* If the Busy Functionality is not implemented, don't handle it */
650 if (data->uart_16550_compatible)
651 p->handle_irq = NULL;
652
653 if (!data->skip_autocfg)
654 dw8250_setup_port(p);
655
656 /* If we have a valid fifosize, try hooking up DMA */
657 if (p->fifosize) {
658 data->data.dma.rxconf.src_maxburst = p->fifosize / 4;
659 data->data.dma.txconf.dst_maxburst = p->fifosize / 4;
660 up->dma = &data->data.dma;
661 }
662
663 data->data.line = serial8250_register_8250_port(up);
664 if (data->data.line < 0)
665 return data->data.line;
666
667 /*
668 * Some platforms may provide a reference clock shared between several
669 * devices. In this case any clock state change must be known to the
670 * UART port at least post factum.
671 */
672 if (data->clk) {
673 err = clk_notifier_register(data->clk, &data->clk_notifier);
674 if (err)
675 return dev_err_probe(dev, err, "Failed to set the clock notifier\n");
676 queue_work(system_unbound_wq, &data->clk_work);
677 }
678
679 platform_set_drvdata(pdev, data);
680
681 pm_runtime_set_active(dev);
682 pm_runtime_enable(dev);
683
684 return 0;
685 }
686
dw8250_remove(struct platform_device * pdev)687 static int dw8250_remove(struct platform_device *pdev)
688 {
689 struct dw8250_data *data = platform_get_drvdata(pdev);
690 struct device *dev = &pdev->dev;
691
692 pm_runtime_get_sync(dev);
693
694 if (data->clk) {
695 clk_notifier_unregister(data->clk, &data->clk_notifier);
696
697 flush_work(&data->clk_work);
698 }
699
700 serial8250_unregister_port(data->data.line);
701
702 pm_runtime_disable(dev);
703 pm_runtime_put_noidle(dev);
704
705 return 0;
706 }
707
dw8250_suspend(struct device * dev)708 static int dw8250_suspend(struct device *dev)
709 {
710 struct dw8250_data *data = dev_get_drvdata(dev);
711
712 serial8250_suspend_port(data->data.line);
713
714 return 0;
715 }
716
dw8250_resume(struct device * dev)717 static int dw8250_resume(struct device *dev)
718 {
719 struct dw8250_data *data = dev_get_drvdata(dev);
720
721 serial8250_resume_port(data->data.line);
722
723 return 0;
724 }
725
dw8250_runtime_suspend(struct device * dev)726 static int dw8250_runtime_suspend(struct device *dev)
727 {
728 struct dw8250_data *data = dev_get_drvdata(dev);
729
730 clk_disable_unprepare(data->clk);
731
732 clk_disable_unprepare(data->pclk);
733
734 return 0;
735 }
736
dw8250_runtime_resume(struct device * dev)737 static int dw8250_runtime_resume(struct device *dev)
738 {
739 struct dw8250_data *data = dev_get_drvdata(dev);
740
741 clk_prepare_enable(data->pclk);
742
743 clk_prepare_enable(data->clk);
744
745 return 0;
746 }
747
748 static const struct dev_pm_ops dw8250_pm_ops = {
749 SYSTEM_SLEEP_PM_OPS(dw8250_suspend, dw8250_resume)
750 RUNTIME_PM_OPS(dw8250_runtime_suspend, dw8250_runtime_resume, NULL)
751 };
752
753 static const struct dw8250_platform_data dw8250_dw_apb = {
754 .usr_reg = DW_UART_USR,
755 };
756
757 static const struct dw8250_platform_data dw8250_octeon_3860_data = {
758 .usr_reg = OCTEON_UART_USR,
759 .quirks = DW_UART_QUIRK_OCTEON,
760 };
761
762 static const struct dw8250_platform_data dw8250_armada_38x_data = {
763 .usr_reg = DW_UART_USR,
764 .quirks = DW_UART_QUIRK_ARMADA_38X,
765 };
766
767 static const struct dw8250_platform_data dw8250_renesas_rzn1_data = {
768 .usr_reg = DW_UART_USR,
769 .cpr_val = 0x00012f32,
770 .quirks = DW_UART_QUIRK_IS_DMA_FC,
771 };
772
773 static const struct dw8250_platform_data dw8250_starfive_jh7100_data = {
774 .usr_reg = DW_UART_USR,
775 .quirks = DW_UART_QUIRK_SKIP_SET_RATE,
776 };
777
778 static const struct of_device_id dw8250_of_match[] = {
779 { .compatible = "snps,dw-apb-uart", .data = &dw8250_dw_apb },
780 { .compatible = "cavium,octeon-3860-uart", .data = &dw8250_octeon_3860_data },
781 { .compatible = "marvell,armada-38x-uart", .data = &dw8250_armada_38x_data },
782 { .compatible = "renesas,rzn1-uart", .data = &dw8250_renesas_rzn1_data },
783 { .compatible = "starfive,jh7100-uart", .data = &dw8250_starfive_jh7100_data },
784 { /* Sentinel */ }
785 };
786 MODULE_DEVICE_TABLE(of, dw8250_of_match);
787
788 static const struct acpi_device_id dw8250_acpi_match[] = {
789 { "80860F0A", (kernel_ulong_t)&dw8250_dw_apb },
790 { "8086228A", (kernel_ulong_t)&dw8250_dw_apb },
791 { "AMD0020", (kernel_ulong_t)&dw8250_dw_apb },
792 { "AMDI0020", (kernel_ulong_t)&dw8250_dw_apb },
793 { "AMDI0022", (kernel_ulong_t)&dw8250_dw_apb },
794 { "APMC0D08", (kernel_ulong_t)&dw8250_dw_apb},
795 { "BRCM2032", (kernel_ulong_t)&dw8250_dw_apb },
796 { "HISI0031", (kernel_ulong_t)&dw8250_dw_apb },
797 { "INT33C4", (kernel_ulong_t)&dw8250_dw_apb },
798 { "INT33C5", (kernel_ulong_t)&dw8250_dw_apb },
799 { "INT3434", (kernel_ulong_t)&dw8250_dw_apb },
800 { "INT3435", (kernel_ulong_t)&dw8250_dw_apb },
801 { },
802 };
803 MODULE_DEVICE_TABLE(acpi, dw8250_acpi_match);
804
805 static struct platform_driver dw8250_platform_driver = {
806 .driver = {
807 .name = "dw-apb-uart",
808 .pm = pm_ptr(&dw8250_pm_ops),
809 .of_match_table = dw8250_of_match,
810 .acpi_match_table = dw8250_acpi_match,
811 },
812 .probe = dw8250_probe,
813 .remove = dw8250_remove,
814 };
815
816 module_platform_driver(dw8250_platform_driver);
817
818 MODULE_AUTHOR("Jamie Iles");
819 MODULE_LICENSE("GPL");
820 MODULE_DESCRIPTION("Synopsys DesignWare 8250 serial port driver");
821 MODULE_ALIAS("platform:dw-apb-uart");
822
