1 /*
2 * IIO driver for the ACCES 104-QUAD-8
3 * Copyright (C) 2016 William Breathitt Gray
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License, version 2, as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
13 *
14 * This driver supports the ACCES 104-QUAD-8 and ACCES 104-QUAD-4.
15 */
16 #include <linux/bitops.h>
17 #include <linux/device.h>
18 #include <linux/errno.h>
19 #include <linux/iio/iio.h>
20 #include <linux/iio/types.h>
21 #include <linux/io.h>
22 #include <linux/ioport.h>
23 #include <linux/isa.h>
24 #include <linux/kernel.h>
25 #include <linux/module.h>
26 #include <linux/moduleparam.h>
27 #include <linux/types.h>
28
29 #define QUAD8_EXTENT 32
30
31 static unsigned int base[max_num_isa_dev(QUAD8_EXTENT)];
32 static unsigned int num_quad8;
33 module_param_array(base, uint, &num_quad8, 0);
34 MODULE_PARM_DESC(base, "ACCES 104-QUAD-8 base addresses");
35
36 #define QUAD8_NUM_COUNTERS 8
37
38 /**
39 * struct quad8_iio - IIO device private data structure
40 * @preset: array of preset values
41 * @count_mode: array of count mode configurations
42 * @quadrature_mode: array of quadrature mode configurations
43 * @quadrature_scale: array of quadrature mode scale configurations
44 * @ab_enable: array of A and B inputs enable configurations
45 * @preset_enable: array of set_to_preset_on_index attribute configurations
46 * @synchronous_mode: array of index function synchronous mode configurations
47 * @index_polarity: array of index function polarity configurations
48 * @base: base port address of the IIO device
49 */
50 struct quad8_iio {
51 unsigned int preset[QUAD8_NUM_COUNTERS];
52 unsigned int count_mode[QUAD8_NUM_COUNTERS];
53 unsigned int quadrature_mode[QUAD8_NUM_COUNTERS];
54 unsigned int quadrature_scale[QUAD8_NUM_COUNTERS];
55 unsigned int ab_enable[QUAD8_NUM_COUNTERS];
56 unsigned int preset_enable[QUAD8_NUM_COUNTERS];
57 unsigned int synchronous_mode[QUAD8_NUM_COUNTERS];
58 unsigned int index_polarity[QUAD8_NUM_COUNTERS];
59 unsigned int base;
60 };
61
62 #define QUAD8_REG_CHAN_OP 0x11
63 #define QUAD8_REG_INDEX_INPUT_LEVELS 0x16
64 /* Borrow Toggle flip-flop */
65 #define QUAD8_FLAG_BT BIT(0)
66 /* Carry Toggle flip-flop */
67 #define QUAD8_FLAG_CT BIT(1)
68 /* Error flag */
69 #define QUAD8_FLAG_E BIT(4)
70 /* Up/Down flag */
71 #define QUAD8_FLAG_UD BIT(5)
72 /* Reset and Load Signal Decoders */
73 #define QUAD8_CTR_RLD 0x00
74 /* Counter Mode Register */
75 #define QUAD8_CTR_CMR 0x20
76 /* Input / Output Control Register */
77 #define QUAD8_CTR_IOR 0x40
78 /* Index Control Register */
79 #define QUAD8_CTR_IDR 0x60
80 /* Reset Byte Pointer (three byte data pointer) */
81 #define QUAD8_RLD_RESET_BP 0x01
82 /* Reset Counter */
83 #define QUAD8_RLD_RESET_CNTR 0x02
84 /* Reset Borrow Toggle, Carry Toggle, Compare Toggle, and Sign flags */
85 #define QUAD8_RLD_RESET_FLAGS 0x04
86 /* Reset Error flag */
87 #define QUAD8_RLD_RESET_E 0x06
88 /* Preset Register to Counter */
89 #define QUAD8_RLD_PRESET_CNTR 0x08
90 /* Transfer Counter to Output Latch */
91 #define QUAD8_RLD_CNTR_OUT 0x10
92 #define QUAD8_CHAN_OP_ENABLE_COUNTERS 0x00
93 #define QUAD8_CHAN_OP_RESET_COUNTERS 0x01
94
quad8_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)95 static int quad8_read_raw(struct iio_dev *indio_dev,
96 struct iio_chan_spec const *chan, int *val, int *val2, long mask)
97 {
98 struct quad8_iio *const priv = iio_priv(indio_dev);
99 const int base_offset = priv->base + 2 * chan->channel;
100 unsigned int flags;
101 unsigned int borrow;
102 unsigned int carry;
103 int i;
104
105 switch (mask) {
106 case IIO_CHAN_INFO_RAW:
107 if (chan->type == IIO_INDEX) {
108 *val = !!(inb(priv->base + QUAD8_REG_INDEX_INPUT_LEVELS)
109 & BIT(chan->channel));
110 return IIO_VAL_INT;
111 }
112
113 flags = inb(base_offset + 1);
114 borrow = flags & QUAD8_FLAG_BT;
115 carry = !!(flags & QUAD8_FLAG_CT);
116
117 /* Borrow XOR Carry effectively doubles count range */
118 *val = (borrow ^ carry) << 24;
119
120 /* Reset Byte Pointer; transfer Counter to Output Latch */
121 outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP | QUAD8_RLD_CNTR_OUT,
122 base_offset + 1);
123
124 for (i = 0; i < 3; i++)
125 *val |= (unsigned int)inb(base_offset) << (8 * i);
126
127 return IIO_VAL_INT;
128 case IIO_CHAN_INFO_ENABLE:
129 *val = priv->ab_enable[chan->channel];
130 return IIO_VAL_INT;
131 case IIO_CHAN_INFO_SCALE:
132 *val = 1;
133 *val2 = priv->quadrature_scale[chan->channel];
134 return IIO_VAL_FRACTIONAL_LOG2;
135 }
136
137 return -EINVAL;
138 }
139
quad8_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long mask)140 static int quad8_write_raw(struct iio_dev *indio_dev,
141 struct iio_chan_spec const *chan, int val, int val2, long mask)
142 {
143 struct quad8_iio *const priv = iio_priv(indio_dev);
144 const int base_offset = priv->base + 2 * chan->channel;
145 int i;
146 unsigned int ior_cfg;
147
148 switch (mask) {
149 case IIO_CHAN_INFO_RAW:
150 if (chan->type == IIO_INDEX)
151 return -EINVAL;
152
153 /* Only 24-bit values are supported */
154 if ((unsigned int)val > 0xFFFFFF)
155 return -EINVAL;
156
157 /* Reset Byte Pointer */
158 outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1);
159
160 /* Counter can only be set via Preset Register */
161 for (i = 0; i < 3; i++)
162 outb(val >> (8 * i), base_offset);
163
164 /* Transfer Preset Register to Counter */
165 outb(QUAD8_CTR_RLD | QUAD8_RLD_PRESET_CNTR, base_offset + 1);
166
167 /* Reset Byte Pointer */
168 outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1);
169
170 /* Set Preset Register back to original value */
171 val = priv->preset[chan->channel];
172 for (i = 0; i < 3; i++)
173 outb(val >> (8 * i), base_offset);
174
175 /* Reset Borrow, Carry, Compare, and Sign flags */
176 outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_FLAGS, base_offset + 1);
177 /* Reset Error flag */
178 outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_E, base_offset + 1);
179
180 return 0;
181 case IIO_CHAN_INFO_ENABLE:
182 /* only boolean values accepted */
183 if (val < 0 || val > 1)
184 return -EINVAL;
185
186 priv->ab_enable[chan->channel] = val;
187
188 ior_cfg = val | priv->preset_enable[chan->channel] << 1;
189
190 /* Load I/O control configuration */
191 outb(QUAD8_CTR_IOR | ior_cfg, base_offset + 1);
192
193 return 0;
194 case IIO_CHAN_INFO_SCALE:
195 /* Quadrature scaling only available in quadrature mode */
196 if (!priv->quadrature_mode[chan->channel] && (val2 || val != 1))
197 return -EINVAL;
198
199 /* Only three gain states (1, 0.5, 0.25) */
200 if (val == 1 && !val2)
201 priv->quadrature_scale[chan->channel] = 0;
202 else if (!val)
203 switch (val2) {
204 case 500000:
205 priv->quadrature_scale[chan->channel] = 1;
206 break;
207 case 250000:
208 priv->quadrature_scale[chan->channel] = 2;
209 break;
210 default:
211 return -EINVAL;
212 }
213 else
214 return -EINVAL;
215
216 return 0;
217 }
218
219 return -EINVAL;
220 }
221
222 static const struct iio_info quad8_info = {
223 .read_raw = quad8_read_raw,
224 .write_raw = quad8_write_raw
225 };
226
quad8_read_preset(struct iio_dev * indio_dev,uintptr_t private,const struct iio_chan_spec * chan,char * buf)227 static ssize_t quad8_read_preset(struct iio_dev *indio_dev, uintptr_t private,
228 const struct iio_chan_spec *chan, char *buf)
229 {
230 const struct quad8_iio *const priv = iio_priv(indio_dev);
231
232 return snprintf(buf, PAGE_SIZE, "%u\n", priv->preset[chan->channel]);
233 }
234
quad8_write_preset(struct iio_dev * indio_dev,uintptr_t private,const struct iio_chan_spec * chan,const char * buf,size_t len)235 static ssize_t quad8_write_preset(struct iio_dev *indio_dev, uintptr_t private,
236 const struct iio_chan_spec *chan, const char *buf, size_t len)
237 {
238 struct quad8_iio *const priv = iio_priv(indio_dev);
239 const int base_offset = priv->base + 2 * chan->channel;
240 unsigned int preset;
241 int ret;
242 int i;
243
244 ret = kstrtouint(buf, 0, &preset);
245 if (ret)
246 return ret;
247
248 /* Only 24-bit values are supported */
249 if (preset > 0xFFFFFF)
250 return -EINVAL;
251
252 priv->preset[chan->channel] = preset;
253
254 /* Reset Byte Pointer */
255 outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1);
256
257 /* Set Preset Register */
258 for (i = 0; i < 3; i++)
259 outb(preset >> (8 * i), base_offset);
260
261 return len;
262 }
263
quad8_read_set_to_preset_on_index(struct iio_dev * indio_dev,uintptr_t private,const struct iio_chan_spec * chan,char * buf)264 static ssize_t quad8_read_set_to_preset_on_index(struct iio_dev *indio_dev,
265 uintptr_t private, const struct iio_chan_spec *chan, char *buf)
266 {
267 const struct quad8_iio *const priv = iio_priv(indio_dev);
268
269 return snprintf(buf, PAGE_SIZE, "%u\n",
270 !priv->preset_enable[chan->channel]);
271 }
272
quad8_write_set_to_preset_on_index(struct iio_dev * indio_dev,uintptr_t private,const struct iio_chan_spec * chan,const char * buf,size_t len)273 static ssize_t quad8_write_set_to_preset_on_index(struct iio_dev *indio_dev,
274 uintptr_t private, const struct iio_chan_spec *chan, const char *buf,
275 size_t len)
276 {
277 struct quad8_iio *const priv = iio_priv(indio_dev);
278 const int base_offset = priv->base + 2 * chan->channel + 1;
279 bool preset_enable;
280 int ret;
281 unsigned int ior_cfg;
282
283 ret = kstrtobool(buf, &preset_enable);
284 if (ret)
285 return ret;
286
287 /* Preset enable is active low in Input/Output Control register */
288 preset_enable = !preset_enable;
289
290 priv->preset_enable[chan->channel] = preset_enable;
291
292 ior_cfg = priv->ab_enable[chan->channel] |
293 (unsigned int)preset_enable << 1;
294
295 /* Load I/O control configuration to Input / Output Control Register */
296 outb(QUAD8_CTR_IOR | ior_cfg, base_offset);
297
298 return len;
299 }
300
301 static const char *const quad8_noise_error_states[] = {
302 "No excessive noise is present at the count inputs",
303 "Excessive noise is present at the count inputs"
304 };
305
quad8_get_noise_error(struct iio_dev * indio_dev,const struct iio_chan_spec * chan)306 static int quad8_get_noise_error(struct iio_dev *indio_dev,
307 const struct iio_chan_spec *chan)
308 {
309 struct quad8_iio *const priv = iio_priv(indio_dev);
310 const int base_offset = priv->base + 2 * chan->channel + 1;
311
312 return !!(inb(base_offset) & QUAD8_FLAG_E);
313 }
314
315 static const struct iio_enum quad8_noise_error_enum = {
316 .items = quad8_noise_error_states,
317 .num_items = ARRAY_SIZE(quad8_noise_error_states),
318 .get = quad8_get_noise_error
319 };
320
321 static const char *const quad8_count_direction_states[] = {
322 "down",
323 "up"
324 };
325
quad8_get_count_direction(struct iio_dev * indio_dev,const struct iio_chan_spec * chan)326 static int quad8_get_count_direction(struct iio_dev *indio_dev,
327 const struct iio_chan_spec *chan)
328 {
329 struct quad8_iio *const priv = iio_priv(indio_dev);
330 const int base_offset = priv->base + 2 * chan->channel + 1;
331
332 return !!(inb(base_offset) & QUAD8_FLAG_UD);
333 }
334
335 static const struct iio_enum quad8_count_direction_enum = {
336 .items = quad8_count_direction_states,
337 .num_items = ARRAY_SIZE(quad8_count_direction_states),
338 .get = quad8_get_count_direction
339 };
340
341 static const char *const quad8_count_modes[] = {
342 "normal",
343 "range limit",
344 "non-recycle",
345 "modulo-n"
346 };
347
quad8_set_count_mode(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,unsigned int count_mode)348 static int quad8_set_count_mode(struct iio_dev *indio_dev,
349 const struct iio_chan_spec *chan, unsigned int count_mode)
350 {
351 struct quad8_iio *const priv = iio_priv(indio_dev);
352 unsigned int mode_cfg = count_mode << 1;
353 const int base_offset = priv->base + 2 * chan->channel + 1;
354
355 priv->count_mode[chan->channel] = count_mode;
356
357 /* Add quadrature mode configuration */
358 if (priv->quadrature_mode[chan->channel])
359 mode_cfg |= (priv->quadrature_scale[chan->channel] + 1) << 3;
360
361 /* Load mode configuration to Counter Mode Register */
362 outb(QUAD8_CTR_CMR | mode_cfg, base_offset);
363
364 return 0;
365 }
366
quad8_get_count_mode(struct iio_dev * indio_dev,const struct iio_chan_spec * chan)367 static int quad8_get_count_mode(struct iio_dev *indio_dev,
368 const struct iio_chan_spec *chan)
369 {
370 const struct quad8_iio *const priv = iio_priv(indio_dev);
371
372 return priv->count_mode[chan->channel];
373 }
374
375 static const struct iio_enum quad8_count_mode_enum = {
376 .items = quad8_count_modes,
377 .num_items = ARRAY_SIZE(quad8_count_modes),
378 .set = quad8_set_count_mode,
379 .get = quad8_get_count_mode
380 };
381
382 static const char *const quad8_synchronous_modes[] = {
383 "non-synchronous",
384 "synchronous"
385 };
386
quad8_set_synchronous_mode(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,unsigned int synchronous_mode)387 static int quad8_set_synchronous_mode(struct iio_dev *indio_dev,
388 const struct iio_chan_spec *chan, unsigned int synchronous_mode)
389 {
390 struct quad8_iio *const priv = iio_priv(indio_dev);
391 const unsigned int idr_cfg = synchronous_mode |
392 priv->index_polarity[chan->channel] << 1;
393 const int base_offset = priv->base + 2 * chan->channel + 1;
394
395 /* Index function must be non-synchronous in non-quadrature mode */
396 if (synchronous_mode && !priv->quadrature_mode[chan->channel])
397 return -EINVAL;
398
399 priv->synchronous_mode[chan->channel] = synchronous_mode;
400
401 /* Load Index Control configuration to Index Control Register */
402 outb(QUAD8_CTR_IDR | idr_cfg, base_offset);
403
404 return 0;
405 }
406
quad8_get_synchronous_mode(struct iio_dev * indio_dev,const struct iio_chan_spec * chan)407 static int quad8_get_synchronous_mode(struct iio_dev *indio_dev,
408 const struct iio_chan_spec *chan)
409 {
410 const struct quad8_iio *const priv = iio_priv(indio_dev);
411
412 return priv->synchronous_mode[chan->channel];
413 }
414
415 static const struct iio_enum quad8_synchronous_mode_enum = {
416 .items = quad8_synchronous_modes,
417 .num_items = ARRAY_SIZE(quad8_synchronous_modes),
418 .set = quad8_set_synchronous_mode,
419 .get = quad8_get_synchronous_mode
420 };
421
422 static const char *const quad8_quadrature_modes[] = {
423 "non-quadrature",
424 "quadrature"
425 };
426
quad8_set_quadrature_mode(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,unsigned int quadrature_mode)427 static int quad8_set_quadrature_mode(struct iio_dev *indio_dev,
428 const struct iio_chan_spec *chan, unsigned int quadrature_mode)
429 {
430 struct quad8_iio *const priv = iio_priv(indio_dev);
431 unsigned int mode_cfg = priv->count_mode[chan->channel] << 1;
432 const int base_offset = priv->base + 2 * chan->channel + 1;
433
434 if (quadrature_mode)
435 mode_cfg |= (priv->quadrature_scale[chan->channel] + 1) << 3;
436 else {
437 /* Quadrature scaling only available in quadrature mode */
438 priv->quadrature_scale[chan->channel] = 0;
439
440 /* Synchronous function not supported in non-quadrature mode */
441 if (priv->synchronous_mode[chan->channel])
442 quad8_set_synchronous_mode(indio_dev, chan, 0);
443 }
444
445 priv->quadrature_mode[chan->channel] = quadrature_mode;
446
447 /* Load mode configuration to Counter Mode Register */
448 outb(QUAD8_CTR_CMR | mode_cfg, base_offset);
449
450 return 0;
451 }
452
quad8_get_quadrature_mode(struct iio_dev * indio_dev,const struct iio_chan_spec * chan)453 static int quad8_get_quadrature_mode(struct iio_dev *indio_dev,
454 const struct iio_chan_spec *chan)
455 {
456 const struct quad8_iio *const priv = iio_priv(indio_dev);
457
458 return priv->quadrature_mode[chan->channel];
459 }
460
461 static const struct iio_enum quad8_quadrature_mode_enum = {
462 .items = quad8_quadrature_modes,
463 .num_items = ARRAY_SIZE(quad8_quadrature_modes),
464 .set = quad8_set_quadrature_mode,
465 .get = quad8_get_quadrature_mode
466 };
467
468 static const char *const quad8_index_polarity_modes[] = {
469 "negative",
470 "positive"
471 };
472
quad8_set_index_polarity(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,unsigned int index_polarity)473 static int quad8_set_index_polarity(struct iio_dev *indio_dev,
474 const struct iio_chan_spec *chan, unsigned int index_polarity)
475 {
476 struct quad8_iio *const priv = iio_priv(indio_dev);
477 const unsigned int idr_cfg = priv->synchronous_mode[chan->channel] |
478 index_polarity << 1;
479 const int base_offset = priv->base + 2 * chan->channel + 1;
480
481 priv->index_polarity[chan->channel] = index_polarity;
482
483 /* Load Index Control configuration to Index Control Register */
484 outb(QUAD8_CTR_IDR | idr_cfg, base_offset);
485
486 return 0;
487 }
488
quad8_get_index_polarity(struct iio_dev * indio_dev,const struct iio_chan_spec * chan)489 static int quad8_get_index_polarity(struct iio_dev *indio_dev,
490 const struct iio_chan_spec *chan)
491 {
492 const struct quad8_iio *const priv = iio_priv(indio_dev);
493
494 return priv->index_polarity[chan->channel];
495 }
496
497 static const struct iio_enum quad8_index_polarity_enum = {
498 .items = quad8_index_polarity_modes,
499 .num_items = ARRAY_SIZE(quad8_index_polarity_modes),
500 .set = quad8_set_index_polarity,
501 .get = quad8_get_index_polarity
502 };
503
504 static const struct iio_chan_spec_ext_info quad8_count_ext_info[] = {
505 {
506 .name = "preset",
507 .shared = IIO_SEPARATE,
508 .read = quad8_read_preset,
509 .write = quad8_write_preset
510 },
511 {
512 .name = "set_to_preset_on_index",
513 .shared = IIO_SEPARATE,
514 .read = quad8_read_set_to_preset_on_index,
515 .write = quad8_write_set_to_preset_on_index
516 },
517 IIO_ENUM("noise_error", IIO_SEPARATE, &quad8_noise_error_enum),
518 IIO_ENUM_AVAILABLE("noise_error", &quad8_noise_error_enum),
519 IIO_ENUM("count_direction", IIO_SEPARATE, &quad8_count_direction_enum),
520 IIO_ENUM_AVAILABLE("count_direction", &quad8_count_direction_enum),
521 IIO_ENUM("count_mode", IIO_SEPARATE, &quad8_count_mode_enum),
522 IIO_ENUM_AVAILABLE("count_mode", &quad8_count_mode_enum),
523 IIO_ENUM("quadrature_mode", IIO_SEPARATE, &quad8_quadrature_mode_enum),
524 IIO_ENUM_AVAILABLE("quadrature_mode", &quad8_quadrature_mode_enum),
525 {}
526 };
527
528 static const struct iio_chan_spec_ext_info quad8_index_ext_info[] = {
529 IIO_ENUM("synchronous_mode", IIO_SEPARATE,
530 &quad8_synchronous_mode_enum),
531 IIO_ENUM_AVAILABLE("synchronous_mode", &quad8_synchronous_mode_enum),
532 IIO_ENUM("index_polarity", IIO_SEPARATE, &quad8_index_polarity_enum),
533 IIO_ENUM_AVAILABLE("index_polarity", &quad8_index_polarity_enum),
534 {}
535 };
536
537 #define QUAD8_COUNT_CHAN(_chan) { \
538 .type = IIO_COUNT, \
539 .channel = (_chan), \
540 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
541 BIT(IIO_CHAN_INFO_ENABLE) | BIT(IIO_CHAN_INFO_SCALE), \
542 .ext_info = quad8_count_ext_info, \
543 .indexed = 1 \
544 }
545
546 #define QUAD8_INDEX_CHAN(_chan) { \
547 .type = IIO_INDEX, \
548 .channel = (_chan), \
549 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
550 .ext_info = quad8_index_ext_info, \
551 .indexed = 1 \
552 }
553
554 static const struct iio_chan_spec quad8_channels[] = {
555 QUAD8_COUNT_CHAN(0), QUAD8_INDEX_CHAN(0),
556 QUAD8_COUNT_CHAN(1), QUAD8_INDEX_CHAN(1),
557 QUAD8_COUNT_CHAN(2), QUAD8_INDEX_CHAN(2),
558 QUAD8_COUNT_CHAN(3), QUAD8_INDEX_CHAN(3),
559 QUAD8_COUNT_CHAN(4), QUAD8_INDEX_CHAN(4),
560 QUAD8_COUNT_CHAN(5), QUAD8_INDEX_CHAN(5),
561 QUAD8_COUNT_CHAN(6), QUAD8_INDEX_CHAN(6),
562 QUAD8_COUNT_CHAN(7), QUAD8_INDEX_CHAN(7)
563 };
564
quad8_probe(struct device * dev,unsigned int id)565 static int quad8_probe(struct device *dev, unsigned int id)
566 {
567 struct iio_dev *indio_dev;
568 struct quad8_iio *priv;
569 int i, j;
570 unsigned int base_offset;
571
572 indio_dev = devm_iio_device_alloc(dev, sizeof(*priv));
573 if (!indio_dev)
574 return -ENOMEM;
575
576 if (!devm_request_region(dev, base[id], QUAD8_EXTENT,
577 dev_name(dev))) {
578 dev_err(dev, "Unable to lock port addresses (0x%X-0x%X)\n",
579 base[id], base[id] + QUAD8_EXTENT);
580 return -EBUSY;
581 }
582
583 indio_dev->info = &quad8_info;
584 indio_dev->modes = INDIO_DIRECT_MODE;
585 indio_dev->num_channels = ARRAY_SIZE(quad8_channels);
586 indio_dev->channels = quad8_channels;
587 indio_dev->name = dev_name(dev);
588 indio_dev->dev.parent = dev;
589
590 priv = iio_priv(indio_dev);
591 priv->base = base[id];
592
593 /* Reset all counters and disable interrupt function */
594 outb(QUAD8_CHAN_OP_RESET_COUNTERS, base[id] + QUAD8_REG_CHAN_OP);
595 /* Set initial configuration for all counters */
596 for (i = 0; i < QUAD8_NUM_COUNTERS; i++) {
597 base_offset = base[id] + 2 * i;
598 /* Reset Byte Pointer */
599 outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1);
600 /* Reset Preset Register */
601 for (j = 0; j < 3; j++)
602 outb(0x00, base_offset);
603 /* Reset Borrow, Carry, Compare, and Sign flags */
604 outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_FLAGS, base_offset + 1);
605 /* Reset Error flag */
606 outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_E, base_offset + 1);
607 /* Binary encoding; Normal count; non-quadrature mode */
608 outb(QUAD8_CTR_CMR, base_offset + 1);
609 /* Disable A and B inputs; preset on index; FLG1 as Carry */
610 outb(QUAD8_CTR_IOR, base_offset + 1);
611 /* Disable index function; negative index polarity */
612 outb(QUAD8_CTR_IDR, base_offset + 1);
613 }
614 /* Enable all counters */
615 outb(QUAD8_CHAN_OP_ENABLE_COUNTERS, base[id] + QUAD8_REG_CHAN_OP);
616
617 return devm_iio_device_register(dev, indio_dev);
618 }
619
620 static struct isa_driver quad8_driver = {
621 .probe = quad8_probe,
622 .driver = {
623 .name = "104-quad-8"
624 }
625 };
626
627 module_isa_driver(quad8_driver, num_quad8);
628
629 MODULE_AUTHOR("William Breathitt Gray <vilhelm.gray@gmail.com>");
630 MODULE_DESCRIPTION("ACCES 104-QUAD-8 IIO driver");
631 MODULE_LICENSE("GPL v2");
632
