1 /*
2 * skl.h - HD Audio skylake defintions.
3 *
4 * Copyright (C) 2015 Intel Corp
5 * Author: Jeeja KP <jeeja.kp@intel.com>
6 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
11 *
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
18 *
19 */
20
21 #ifndef __SOUND_SOC_SKL_H
22 #define __SOUND_SOC_SKL_H
23
24 #include <sound/hda_register.h>
25 #include <sound/hdaudio_ext.h>
26 #include <sound/soc.h>
27 #include "skl-nhlt.h"
28 #include "skl-ssp-clk.h"
29
30 #define SKL_SUSPEND_DELAY 2000
31
32 #define SKL_MAX_ASTATE_CFG 3
33
34 #define AZX_PCIREG_PGCTL 0x44
35 #define AZX_PGCTL_LSRMD_MASK (1 << 4)
36 #define AZX_PGCTL_ADSPPGD BIT(2)
37 #define AZX_PCIREG_CGCTL 0x48
38 #define AZX_CGCTL_MISCBDCGE_MASK (1 << 6)
39 #define AZX_CGCTL_ADSPDCGE BIT(1)
40 /* D0I3C Register fields */
41 #define AZX_REG_VS_D0I3C_CIP 0x1 /* Command in progress */
42 #define AZX_REG_VS_D0I3C_I3 0x4 /* D0i3 enable */
43 #define SKL_MAX_DMACTRL_CFG 18
44 #define DMA_CLK_CONTROLS 1
45 #define DMA_TRANSMITION_START 2
46 #define DMA_TRANSMITION_STOP 3
47
48 #define AZX_REG_VS_EM2_L1SEN BIT(13)
49
50 struct skl_dsp_resource {
51 u32 max_mcps;
52 u32 max_mem;
53 u32 mcps;
54 u32 mem;
55 };
56
57 struct skl_debug;
58
59 struct skl_astate_param {
60 u32 kcps;
61 u32 clk_src;
62 };
63
64 struct skl_astate_config {
65 u32 count;
66 struct skl_astate_param astate_table[0];
67 };
68
69 struct skl_fw_config {
70 struct skl_astate_config *astate_cfg;
71 };
72
73 struct skl {
74 struct hdac_bus hbus;
75 struct pci_dev *pci;
76
77 unsigned int init_done:1; /* delayed init status */
78 struct platform_device *dmic_dev;
79 struct platform_device *i2s_dev;
80 struct platform_device *clk_dev;
81 struct snd_soc_component *component;
82 struct snd_soc_dai_driver *dais;
83
84 struct nhlt_acpi_table *nhlt; /* nhlt ptr */
85 struct skl_sst *skl_sst; /* sst skl ctx */
86
87 struct skl_dsp_resource resource;
88 struct list_head ppl_list;
89 struct list_head bind_list;
90
91 const char *fw_name;
92 char tplg_name[64];
93 unsigned short pci_id;
94 const struct firmware *tplg;
95
96 int supend_active;
97
98 struct work_struct probe_work;
99
100 struct skl_debug *debugfs;
101 u8 nr_modules;
102 struct skl_module **modules;
103 bool use_tplg_pcm;
104 struct skl_fw_config cfg;
105 struct snd_soc_acpi_mach *mach;
106 };
107
108 #define skl_to_bus(s) (&(s)->hbus)
109 #define bus_to_skl(bus) container_of(bus, struct skl, hbus)
110
111 /* to pass dai dma data */
112 struct skl_dma_params {
113 u32 format;
114 u8 stream_tag;
115 };
116
117 struct skl_machine_pdata {
118 u32 dmic_num;
119 bool use_tplg_pcm; /* use dais and dai links from topology */
120 };
121
122 struct skl_dsp_ops {
123 int id;
124 unsigned int num_cores;
125 struct skl_dsp_loader_ops (*loader_ops)(void);
126 int (*init)(struct device *dev, void __iomem *mmio_base,
127 int irq, const char *fw_name,
128 struct skl_dsp_loader_ops loader_ops,
129 struct skl_sst **skl_sst);
130 int (*init_fw)(struct device *dev, struct skl_sst *ctx);
131 void (*cleanup)(struct device *dev, struct skl_sst *ctx);
132 };
133
134 int skl_platform_unregister(struct device *dev);
135 int skl_platform_register(struct device *dev);
136
137 struct nhlt_acpi_table *skl_nhlt_init(struct device *dev);
138 void skl_nhlt_free(struct nhlt_acpi_table *addr);
139 struct nhlt_specific_cfg *skl_get_ep_blob(struct skl *skl, u32 instance,
140 u8 link_type, u8 s_fmt, u8 no_ch,
141 u32 s_rate, u8 dirn, u8 dev_type);
142
143 int skl_get_dmic_geo(struct skl *skl);
144 int skl_nhlt_update_topology_bin(struct skl *skl);
145 int skl_init_dsp(struct skl *skl);
146 int skl_free_dsp(struct skl *skl);
147 int skl_suspend_late_dsp(struct skl *skl);
148 int skl_suspend_dsp(struct skl *skl);
149 int skl_resume_dsp(struct skl *skl);
150 void skl_cleanup_resources(struct skl *skl);
151 const struct skl_dsp_ops *skl_get_dsp_ops(int pci_id);
152 void skl_update_d0i3c(struct device *dev, bool enable);
153 int skl_nhlt_create_sysfs(struct skl *skl);
154 void skl_nhlt_remove_sysfs(struct skl *skl);
155 void skl_get_clks(struct skl *skl, struct skl_ssp_clk *ssp_clks);
156 struct skl_clk_parent_src *skl_get_parent_clk(u8 clk_id);
157 int skl_dsp_set_dma_control(struct skl_sst *ctx, u32 *caps,
158 u32 caps_size, u32 node_id);
159
160 struct skl_module_cfg;
161
162 #ifdef CONFIG_DEBUG_FS
163 struct skl_debug *skl_debugfs_init(struct skl *skl);
164 void skl_debug_init_module(struct skl_debug *d,
165 struct snd_soc_dapm_widget *w,
166 struct skl_module_cfg *mconfig);
167 #else
skl_debugfs_init(struct skl * skl)168 static inline struct skl_debug *skl_debugfs_init(struct skl *skl)
169 {
170 return NULL;
171 }
skl_debug_init_module(struct skl_debug * d,struct snd_soc_dapm_widget * w,struct skl_module_cfg * mconfig)172 static inline void skl_debug_init_module(struct skl_debug *d,
173 struct snd_soc_dapm_widget *w,
174 struct skl_module_cfg *mconfig)
175 {}
176 #endif
177
178 #endif /* __SOUND_SOC_SKL_H */
179
