Searched +full:zynq +full:- +full:spi +full:- +full:r1p6 (Results 1 – 4 of 4) sorted by relevance
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/spi/spi-cadence.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: Cadence SPI controller10 - Michal Simek <michal.simek@xilinx.com>13 - $ref: "spi-controller.yaml#"18 - cdns,spi-r1p619 - xlnx,zynq-spi-r1p627 clock-names:[all …]
1 // SPDX-License-Identifier: GPL-2.03 * Copyright (C) 2011 - 2014 Xilinx7 #address-cells = <1>;8 #size-cells = <1>;9 compatible = "xlnx,zynq-7000";12 #address-cells = <1>;13 #size-cells = <0>;16 compatible = "arm,cortex-a9";20 clock-latency = <1000>;21 cpu0-supply = <®ulator_vccpint>;[all …]
1 // SPDX-License-Identifier: GPL-2.0-or-later3 * Cadence SPI controller driver (master mode only)5 * Copyright (C) 2008 - 2014 Xilinx, Inc.7 * based on Blackfin On-Chip SPI Driver (spi_bfin5xx.c)20 #include <linux/spi/spi.h>23 #define CDNS_SPI_NAME "cdns-spi"40 * SPI Configuration Register bit Masks43 * of the SPI controller61 * SPI Configuration Register - Baud rate and slave select75 * SPI Interrupt Registers bit Masks[all …]
1 // SPDX-License-Identifier: GPL-2.0+5 * (C) Copyright 2014 - 2021, Xilinx, Inc.15 #include <dt-bindings/dma/xlnx-zynqmp-dpdma.h>16 #include <dt-bindings/power/xlnx-zynqmp-power.h>17 #include <dt-bindings/reset/xlnx-zynqmp-resets.h>21 #address-cells = <2>;22 #size-cells = <2>;25 #address-cells = <1>;26 #size-cells = <0>;29 compatible = "arm,cortex-a53";[all …]
