Searched +full:xps +full:- +full:timebase +full:- +full:wdt +full:- +full:1 (Results 1 – 2 of 2) sorted by relevance
1 # SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause3 ---4 $id: http://devicetree.org/schemas/watchdog/xlnx,xps-timebase-wdt.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#10 - Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>11 - Srinivas Neeli <srinivas.neeli@xilinx.com>14 The Timebase watchdog timer(WDT) is a free-running 32 bit counter.15 WDT uses a dual-expiration architecture. After one expiration of16 the timeout interval, an interrupt is generated and the WDT state19 expiration of the timeout interval, a WDT reset is generated.[all …]
1 // SPDX-License-Identifier: GPL-2.0+5 * (C) Copyright 2013 - 2014 Xilinx, Inc.22 /* Register offsets for the Wdt device */25 #define XWT_TBR_OFFSET 0x8 /* Timebase Register Offset */30 #define XWT_CSR0_EWDT1_MASK BIT(1) /* Enable bit 1 */32 /* Control/Status Register 0/1 bits */55 ret = clk_enable(xdev->clk); in xilinx_wdt_start()57 dev_err(wdd->parent, "Failed to enable clock\n"); in xilinx_wdt_start()61 spin_lock(&xdev->spinlock); in xilinx_wdt_start()64 control_status_reg = ioread32(xdev->base + XWT_TWCSR0_OFFSET); in xilinx_wdt_start()[all …]
