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/Linux-v5.10/drivers/pinctrl/mediatek/
Dpinctrl-mt6765.c29 PIN_FIELD(0, 202, 0x300, 0x10, 0, 4),
33 PIN_FIELD(0, 202, 0x0, 0x10, 0, 1),
37 PIN_FIELD(0, 202, 0x200, 0x10, 0, 1),
41 PIN_FIELD(0, 202, 0x100, 0x10, 0, 1),
45 PINS_FIELD_BASE(0, 3, 2, 0x00b0, 0x10, 4, 1),
46 PINS_FIELD_BASE(4, 7, 2, 0x00b0, 0x10, 5, 1),
47 PIN_FIELD_BASE(8, 8, 3, 0x0080, 0x10, 3, 1),
48 PINS_FIELD_BASE(9, 11, 2, 0x00b0, 0x10, 6, 1),
49 PIN_FIELD_BASE(12, 12, 5, 0x0060, 0x10, 9, 1),
50 PINS_FIELD_BASE(13, 16, 6, 0x00b0, 0x10, 10, 1),
[all …]
Dpinctrl-mt6779.c28 PIN_FIELD_BASE(0, 7, 0, 0x0300, 0x10, 0, 4),
29 PIN_FIELD_BASE(8, 15, 0, 0x0310, 0x10, 0, 4),
30 PIN_FIELD_BASE(16, 23, 0, 0x0320, 0x10, 0, 4),
31 PIN_FIELD_BASE(24, 31, 0, 0x0330, 0x10, 0, 4),
32 PIN_FIELD_BASE(32, 39, 0, 0x0340, 0x10, 0, 4),
33 PIN_FIELD_BASE(40, 47, 0, 0x0350, 0x10, 0, 4),
34 PIN_FIELD_BASE(48, 55, 0, 0x0360, 0x10, 0, 4),
35 PIN_FIELD_BASE(56, 63, 0, 0x0370, 0x10, 0, 4),
36 PIN_FIELD_BASE(64, 71, 0, 0x0380, 0x10, 0, 4),
37 PIN_FIELD_BASE(72, 79, 0, 0x0390, 0x10, 0, 4),
[all …]
Dpinctrl-mt8192.c29 PIN_FIELD(0, 228, 0x300, 0x10, 0, 4),
33 PIN_FIELD(0, 228, 0x0, 0x10, 0, 1),
37 PIN_FIELD(0, 228, 0x200, 0x10, 0, 1),
41 PIN_FIELD(0, 228, 0x100, 0x10, 0, 1),
45 PIN_FIELD_BASE(0, 0, 4, 0x00f0, 0x10, 8, 1),
46 PIN_FIELD_BASE(1, 1, 4, 0x00f0, 0x10, 8, 1),
47 PIN_FIELD_BASE(2, 2, 4, 0x00f0, 0x10, 8, 1),
48 PIN_FIELD_BASE(3, 3, 4, 0x00f0, 0x10, 8, 1),
49 PIN_FIELD_BASE(4, 4, 4, 0x00f0, 0x10, 8, 1),
50 PIN_FIELD_BASE(5, 5, 4, 0x00f0, 0x10, 9, 1),
[all …]
Dpinctrl-mt8183.c28 PIN_FIELD(0, 192, 0x300, 0x10, 0, 4),
32 PIN_FIELD(0, 192, 0x0, 0x10, 0, 1),
36 PIN_FIELD(0, 192, 0x200, 0x10, 0, 1),
40 PIN_FIELD(0, 192, 0x100, 0x10, 0, 1),
44 PINS_FIELD_BASE(0, 3, 6, 0x000, 0x10, 3, 1),
45 PINS_FIELD_BASE(4, 7, 6, 0x000, 0x10, 5, 1),
46 PIN_FIELD_BASE(8, 8, 6, 0x000, 0x10, 0, 1),
47 PINS_FIELD_BASE(9, 10, 6, 0x000, 0x10, 12, 1),
48 PIN_FIELD_BASE(11, 11, 1, 0x000, 0x10, 3, 1),
49 PIN_FIELD_BASE(12, 12, 1, 0x000, 0x10, 7, 1),
[all …]
Dpinctrl-mt7623.c36 PIN_FIELD15(0, 278, 0x760, 0x10, 0, 3),
40 PIN_FIELD16(0, 175, 0x0, 0x10, 0, 1),
41 PIN_FIELD16(176, 278, 0xc0, 0x10, 0, 1),
45 PIN_FIELD16(0, 278, 0x630, 0x10, 0, 1),
49 PIN_FIELD16(0, 278, 0x500, 0x10, 0, 1),
53 PINS_FIELD16(0, 6, 0xb20, 0x10, 0, 1),
54 PINS_FIELD16(7, 9, 0xb20, 0x10, 1, 1),
55 PINS_FIELD16(10, 13, 0xb30, 0x10, 3, 1),
56 PINS_FIELD16(14, 15, 0xb30, 0x10, 13, 1),
57 PINS_FIELD16(16, 17, 0xb40, 0x10, 7, 1),
[all …]
/Linux-v5.10/fs/unicode/
Dutf8data.h_shipped97 0xe1,0x8d,0xa9,0x10,0x08,0x01,0xff,0xe8,0xb1,0x88,0x00,0x01,0xff,0xe6,0x9b,0xb4,
99 0xab,0x10,0x08,0x01,0xff,0xe9,0xb9,0xbf,0x00,0x01,0xff,0xe8,0xab,0x96,0x00,0xe3,
100 0x09,0xac,0xe2,0xe8,0xab,0xe1,0xd7,0xab,0x10,0x08,0x01,0xff,0xe7,0xb8,0xb7,0x00,
110 0x4e,0xe3,0xe2,0x2d,0xe3,0xe1,0x1b,0xe3,0x10,0x08,0x05,0xff,0xe4,0xb8,0xbd,0x00,
112 0xe2,0x0e,0xe5,0xe1,0xfd,0xe4,0x10,0x08,0x05,0xff,0xe5,0x92,0xa2,0x00,0x05,0xff,
113 0xe5,0x93,0xb6,0x00,0xd4,0x34,0xd3,0x18,0xe2,0xf7,0xe5,0xe1,0xe6,0xe5,0x10,0x09,
115 0xe6,0x91,0x11,0x10,0x09,0x05,0xff,0xf0,0xa1,0x8d,0xaa,0x00,0x05,0xff,0xe5,0xac,
117 0x10,0x08,0x05,0xff,0xe5,0xaf,0xb3,0x00,0x05,0xff,0xf0,0xa1,0xac,0x98,0x00,0xe1,
118 0x38,0xe6,0x10,0x08,0x05,0xff,0xe5,0xbc,0xb3,0x00,0x05,0xff,0xe5,0xb0,0xa2,0x00,
120 0xea,0xe1,0x93,0xea,0x10,0x08,0x05,0xff,0xe6,0xb4,0xbe,0x00,0x05,0xff,0xe6,0xb5,
[all …]
/Linux-v5.10/include/linux/mlx5/
Dmlx5_ifc.h50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10,
442 u8 reserved_at_a8[0x10];
465 u8 smac_15_0[0x10];
466 u8 ethertype[0x10];
470 u8 dmac_15_0[0x10];
484 u8 tcp_sport[0x10];
485 u8 tcp_dport[0x10];
490 u8 udp_sport[0x10];
491 u8 udp_dport[0x10];
516 u8 source_eswitch_owner_vhca_id[0x10];
[all …]
/Linux-v5.10/drivers/media/usb/gspca/
Dsonixj.c357 {0xa0, 0x51, 0xfe, 0x00, 0x00, 0x00, 0x00, 0x10},
358 {0xb0, 0x51, 0x04, 0x08, 0x00, 0x00, 0x00, 0x10}, /* reset */
360 {0xb0, 0x51, 0x04, 0x00, 0x00, 0x00, 0x00, 0x10},
362 {0xb0, 0x51, 0x0c, 0xe0, 0x2e, 0x00, 0x00, 0x10},
363 {0xb0, 0x51, 0x10, 0x02, 0x02, 0x00, 0x00, 0x10},
364 {0xb0, 0x51, 0x14, 0x0e, 0x0e, 0x00, 0x00, 0x10},
365 {0xb0, 0x51, 0x1c, 0x00, 0x80, 0x00, 0x00, 0x10},
366 {0xb0, 0x51, 0x20, 0x01, 0x00, 0x00, 0x00, 0x10},
368 {0xb0, 0x51, 0x04, 0x04, 0x00, 0x00, 0x00, 0x10},
370 {0xb0, 0x51, 0x04, 0x01, 0x00, 0x00, 0x00, 0x10},
[all …]
Dnw80x.c174 0x00, 0x00, 0x40, 0x10, 0x43, 0x00, 0xb4, 0x01, 0x10, 0x00, 0x4f,
187 0x04, 0x10, 0x00, 0x36, 0x00, 0xd2, 0x00, 0xee,
198 0x04, 0x00, 0x07, 0x01, 0x10, 0x00, 0x00, 0x00, 0x61, 0xc0,
207 0x10, 0x00, 0x40, 0x83, 0x02, 0x20, 0x00, 0x13, 0x00, 0x00, 0x00,
208 0x00, 0x00, 0x00, 0x10, 0x10, 0x10, 0x08, 0x0a,
212 0x00, 0x20, 0x00, 0x00, 0x00, 0x20, 0x10, 0x08,
213 0x03, 0x00, 0x00, 0x00, 0x00, 0x20, 0x10, 0x06,
214 0xf7, 0xee, 0x1c, 0x1c, 0xe9, 0xfc, 0x10, 0x80,
215 0x10, 0x40, 0x40, 0x80, 0x00, 0x05, 0x35, 0x5e, 0x78, 0x8b, 0x99,
223 0x10, 0x80, 0x1d, 0xc3, 0xd2, 0xe2, 0xf1, 0xff, 0x00, 0x00, 0x00,
[all …]
/Linux-v5.10/lib/fonts/
Dfont_6x8.c44 0x10, /* 000100 */
50 0x10, /* 000100 */
54 0x10, /* 000100 */
64 0x10, /* 000100 */
70 0x10, /* 000100 */
74 0x10, /* 000100 */
133 0x10, /* 000100 */
135 0x10, /* 000100 */
142 0x10, /* 000100 */
143 0x10, /* 000100 */
[all …]
Dfont_6x10.c51 0x10, /* 00010000 */
59 0x10, /* 00010000 */
63 0x10, /* 00010000 */
75 0x10, /* 00010000 */
83 0x10, /* 00010000 */
87 0x10, /* 00010000 */
158 0x10, /* 00010000 */
160 0x10, /* 00010000 */
169 0x10, /* 00010000 */
170 0x10, /* 00010000 */
[all …]
Dfont_6x11.c60 0x10, /* 000 0000 */
69 0x10, /* 000 0000 */
73 0x10, /* 000 0000 */
86 0x10, /* 000 0000 */
95 0x10, /* 000 0000 */
99 0x10, /* 000 0000 */
176 0x10, /* 000 0000 */
178 0x10, /* 000 0000 */
211 0x10, /* 000 0000 */
217 0x10, /* 000 0000 */
[all …]
/Linux-v5.10/arch/x86/crypto/
Daegis128-aesni-asm.S95 shl $0x10, %r9
118 and $0x10, %r8
171 shr $0x10, %r10
222 movdqu STATE1, 0x10(STATEP)
238 cmp $0x10, LEN
243 movdqu 0x10(STATEP), STATE1
257 sub $0x10, LEN
258 cmp $0x10, LEN
261 movdqa 0x10(SRC), MSG
264 sub $0x10, LEN
[all …]
/Linux-v5.10/drivers/gpu/drm/amd/include/asic_reg/dce/
Ddce_8_0_sh_mask.h124 #define DC_PGCNTL_STATUS_REG__DCPG_ECO_DEBUG__SHIFT 0x10
152 #define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE__SHIFT 0x10
160 …PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x10
168 #define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START__SHIFT 0x10
186 #define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R__SHIFT 0x10
192 #define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0__SHIFT 0x10
198 #define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1__SHIFT 0x10
204 #define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2__SHIFT 0x10
210 #define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3__SHIFT 0x10
216 #define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4__SHIFT 0x10
[all …]
Ddce_11_0_sh_mask.h91 #define DCPG_INTERRUPT_STATUS__DCFE2_POWER_UP_INT_OCCURRED_MASK 0x10
123 #define DCPG_INTERRUPT_CONTROL__DCFE1_POWER_UP_INT_MASK_MASK 0x10
148 #define DCPG_INTERRUPT_CONTROL__DCFE4_POWER_UP_INT_MASK__SHIFT 0x10
192 #define DC_PGCNTL_STATUS_REG__DCPG_ECO_DEBUG__SHIFT 0x10
220 #define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE__SHIFT 0x10
228 …PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x10
236 #define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START__SHIFT 0x10
254 #define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R__SHIFT 0x10
260 #define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0__SHIFT 0x10
266 #define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1__SHIFT 0x10
[all …]
Ddce_11_2_sh_mask.h119 #define DCPG_INTERRUPT_STATUS__DCFE2_POWER_UP_INT_OCCURRED_MASK 0x10
144 #define DCPG_INTERRUPT_STATUS__DCFEV1_POWER_UP_INT_OCCURRED__SHIFT 0x10
155 #define DCPG_INTERRUPT_CONTROL__DCFE1_POWER_UP_INT_MASK_MASK 0x10
180 #define DCPG_INTERRUPT_CONTROL__DCFE4_POWER_UP_INT_MASK__SHIFT 0x10
232 #define DC_PGCNTL_STATUS_REG__DCPG_ECO_DEBUG__SHIFT 0x10
260 #define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE__SHIFT 0x10
268 …PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x10
276 #define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START__SHIFT 0x10
294 #define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R__SHIFT 0x10
300 #define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0__SHIFT 0x10
[all …]
Ddce_10_0_sh_mask.h124 #define DC_PGCNTL_STATUS_REG__DCPG_ECO_DEBUG__SHIFT 0x10
152 #define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE__SHIFT 0x10
160 …PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x10
168 #define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START__SHIFT 0x10
186 #define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R__SHIFT 0x10
192 #define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0__SHIFT 0x10
198 #define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1__SHIFT 0x10
204 #define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2__SHIFT 0x10
210 #define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3__SHIFT 0x10
216 #define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4__SHIFT 0x10
[all …]
/Linux-v5.10/drivers/gpu/drm/amd/include/asic_reg/gmc/
Dgmc_7_1_sh_mask.h35 #define MC_CONFIG__MCDS_WR_ENABLE_MASK 0x10
55 #define MC_ARB_AGE_CNTL__RESET_RD_GROUP4_MASK 0x10
80 #define MC_ARB_AGE_CNTL__AGE_LOW_RATE_RD__SHIFT 0x10
109 #define MC_ARB_FED_CNTL__KEEP_POISON_IN_PAGE_MASK 0x10
125 #define MC_ARB_GECC2_STATUS__CORR_STS1_MASK 0x10
150 #define MC_ARB_GECC2_STATUS__RMWRD_CORR_STS0__SHIFT 0x10
173 #define MC_ARB_GECC2_MISC__COL10_HACK_MASK 0x10
206 #define MC_ARB_GECC2_DEBUG2__ERR1_START__SHIFT 0x10
214 #define MC_ARB_PERF_CID__CH0_EN__SHIFT 0x10
242 #define MC_ARB_GECC2_CLI__NO_GECC_CLI2__SHIFT 0x10
[all …]
Dgmc_8_1_sh_mask.h35 #define MC_CONFIG__MCDS_WR_ENABLE_MASK 0x10
58 #define MC_ARB_ATOMIC__ATOMIC_RTN_GRP__SHIFT 0x10
67 #define MC_ARB_AGE_CNTL__RESET_RD_GROUP4_MASK 0x10
92 #define MC_ARB_AGE_CNTL__AGE_LOW_RATE_RD__SHIFT 0x10
122 #define MC_ARB_RET_CREDITS2__RDRET_CREDIT_MED__SHIFT 0x10
127 #define MC_ARB_FED_CNTL__KEEP_POISON_IN_PAGE_MASK 0x10
143 #define MC_ARB_GECC2_STATUS__CORR_STS1_MASK 0x10
168 #define MC_ARB_GECC2_STATUS__RMWRD_CORR_STS0__SHIFT 0x10
191 #define MC_ARB_GECC2_MISC__COL10_HACK_MASK 0x10
224 #define MC_ARB_GECC2_DEBUG2__ERR1_START__SHIFT 0x10
[all …]
/Linux-v5.10/arch/arm/boot/dts/
Dam335x-pocketbeagle.dts220 pinctrl-single,bias-pullup = < 0x10 0x10 0x00 0x18>;
221 pinctrl-single,bias-pulldown = < 0x10 0x00 0x10 0x18>;
229 pinctrl-single,bias-pullup = < 0x10 0x10 0x00 0x18>;
230 pinctrl-single,bias-pulldown = < 0x10 0x00 0x10 0x18>;
238 pinctrl-single,bias-pullup = < 0x10 0x10 0x00 0x18>;
239 pinctrl-single,bias-pulldown = < 0x10 0x00 0x10 0x18>;
247 pinctrl-single,bias-pullup = < 0x10 0x10 0x00 0x18>;
248 pinctrl-single,bias-pulldown = < 0x10 0x00 0x10 0x18>;
256 pinctrl-single,bias-pullup = < 0x10 0x10 0x00 0x18>;
257 pinctrl-single,bias-pulldown = < 0x10 0x00 0x10 0x18>;
[all …]
/Linux-v5.10/drivers/gpu/drm/amd/include/asic_reg/smu/
Dsmu_7_0_0_sh_mask.h83 #define GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK 0x10
109 #define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_THRU_DFS_MASK 0x10
198 #define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_EN__SHIFT 0x10
215 #define SPLL_CNTL_MODE__SPLL_ENSAT_MASK 0x10
248 #define CG_CLKPIN_CNTL_2__XO_IN_CML_RXEN__SHIFT 0x10
268 #define THM_CLK_CNTL__CTF_CLK_SHUTOFF_EN__SHIFT 0x10
274 #define MISC_CLK_CTRL__DFT_SMS_PG_CLK_SEL__SHIFT 0x10
351 #define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_4_MASK 0x10
482 #define RCU_UC_EVENTS__INTERRUPTS_ENABLED__SHIFT 0x10
495 #define RCU_MISC_CTRL__REG_CC_FUSE_DISABLE_MASK 0x10
[all …]
Dsmu_7_1_2_sh_mask.h83 #define GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK 0x10
109 #define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_THRU_DFS_MASK 0x10
188 #define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_EN__SHIFT 0x10
207 #define SPLL_CNTL_MODE__SPLL_ENSAT_MASK 0x10
240 #define CG_CLKPIN_CNTL_2__XO_IN_CML_RXEN__SHIFT 0x10
266 #define THM_CLK_CNTL__CTF_CLK_SHUTOFF_EN__SHIFT 0x10
272 #define MISC_CLK_CTRL__DFT_SMS_PG_CLK_SEL__SHIFT 0x10
349 #define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_4_MASK 0x10
493 #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_4_MASK 0x10
518 #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_16__SHIFT 0x10
[all …]
/Linux-v5.10/drivers/net/ethernet/mellanox/mlx5/core/steering/
Dmlx5_ifc_dr.h69 MLX5DR_STE_LU_TYPE_ETHL3_IPV6_SRC_I = 0x10,
106 u8 byte_mask[0x10];
108 u8 next_table_base_63_48[0x10];
126 u8 byte_mask[0x10];
128 u8 next_table_base_63_48[0x10];
146 u8 gvmi[0x10];
152 u8 counter_trigger[0x10];
154 u8 miss_address_63_48[0x10];
170 u8 byte_mask[0x10];
172 u8 next_table_base_63_48[0x10];
[all …]
/Linux-v5.10/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_2_0_0_sh_mask.h28 …_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR__SHIFT 0x10
33 …_READ_PAGE_ADDR__VGA_MEM_READ_PAGE1_ADDR__SHIFT 0x10
41 …DER_CONTROL__VGA_VSTATUS_CNTL__SHIFT 0x10
64 …UENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_ENABLE__SHIFT 0x10
86 …E_CONTROL__VGA_TEXT_132_COLUMNS_EN__SHIFT 0x10
114 …_CONTROL__VGA_SOFT_RESET__SHIFT 0x10
124 …HE_CONTROL__VGA_READ_BUFFER_INVALIDATE__SHIFT 0x10
136 …ONTROL__D1VGA_OVERSCAN_COLOR_EN__SHIFT 0x10
147 …ONTROL__D2VGA_OVERSCAN_COLOR_EN__SHIFT 0x10
166 …ERRUPT_CONTROL__VGA_DISPLAY_SWITCH_INT_MASK__SHIFT 0x10
[all …]
Ddcn_3_0_0_sh_mask.h8 …_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR__SHIFT 0x10
13 …_READ_PAGE_ADDR__VGA_MEM_READ_PAGE1_ADDR__SHIFT 0x10
21 …DER_CONTROL__VGA_VSTATUS_CNTL__SHIFT 0x10
44 …UENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_ENABLE__SHIFT 0x10
66 …E_CONTROL__VGA_TEXT_132_COLUMNS_EN__SHIFT 0x10
94 …_CONTROL__VGA_SOFT_RESET__SHIFT 0x10
104 …HE_CONTROL__VGA_READ_BUFFER_INVALIDATE__SHIFT 0x10
116 …ONTROL__D1VGA_OVERSCAN_COLOR_EN__SHIFT 0x10
127 …ONTROL__D2VGA_OVERSCAN_COLOR_EN__SHIFT 0x10
146 …ERRUPT_CONTROL__VGA_DISPLAY_SWITCH_INT_MASK__SHIFT 0x10
[all …]

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