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13 The Rockchip SoC has a MIPI CSI D-PHY based on an Innosilicon IP wich
42 could change at the same time as the limit is written to, wich will lead to
72 * WICH USES THE STREAM2MEMRY BLOCK. in input_formatter_rst()
97 * @ref_inode: inode from wich the super block will be taken
238 /* Invalidate the index wich was cached by the iterator */ in msi_unlock_descs()
1280 on STM32MP1 based platforms, wich default UART is wired on
21 * Include list of clocks wich are not derived from system clock (SYSCLOCK)
17 * Jo-Philipp Wich <jo@mein.io>
