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/Linux-v6.1/tools/perf/pmu-events/arch/x86/elkhartlake/
D	memory.json	36 "BriefDescription": "Counts all code reads that were not supplied by the L3 cache.", 47 "BriefDescription": "Counts all code reads that were not supplied by the L3 cache.", 58 …"BriefDescription": "Counts modified writebacks from L1 cache and L2 cache that were not supplied … 69 …"BriefDescription": "Counts modified writebacks from L1 cache and L2 cache that were not supplied … 80 …ounts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the… 91 …ounts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the… 102 …cache hardware prefetches and software prefetches (except PREFETCHW) that were not supplied by the… 113 …cache hardware prefetches and software prefetches (except PREFETCHW) that were not supplied by the… 146 …ip (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the… 157 …ip (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the… [all …]
D	cache.json	344 "BriefDescription": "Counts the number of memory uops retired that were splits.", 380 "BriefDescription": "Counts all code reads that were supplied by the L3 cache.", 391 …"BriefDescription": "Counts all code reads that were supplied by the L3 cache where a snoop was se… 402 …"BriefDescription": "Counts all code reads that were supplied by the L3 cache where a snoop was se… 413 …"BriefDescription": "Counts all code reads that were supplied by the L3 cache where a snoop was se… 424 …"BriefDescription": "Counts all code reads that were supplied by the L3 cache where a snoop was se… 435 …"BriefDescription": "Counts all code reads that were supplied by the L3 cache where no snoop was n… 446 …"BriefDescription": "Counts modified writebacks from L1 cache and L2 cache that were supplied by t… 457 …ounts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 … 468 …ounts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 … [all …]
D	pipeline.json	366 …"BriefDescription": "Counts the total number of issue slots that were not consumed by the backend … 373 …were not consumed by the backend because allocation is stalled due to a mispredicted jump or a mac… 378 …"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the ba… 389 …"BriefDescription": "Counts the total number of issue slots that were not consumed by the backend … 400 …"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the ba… 422 …"BriefDescription": "Counts the total number of issue slots every cycle that were not consumed by … 432 …"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the ba… 443 …"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the ba… 454 …"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the ba… 465 …"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the ba… [all …]
D	other.json	148 "BriefDescription": "Counts all code reads that were supplied by DRAM.", 159 "BriefDescription": "Counts all code reads that were supplied by DRAM.", 214 …Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM.", 225 …Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM.", 247 … cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by DRAM.", 258 … cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by DRAM.", 335 …hip (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM.", 346 …hip (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM.", 401 … L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by DRAM.", 412 … L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by DRAM.", [all …]
D	virtual-memory.json	31 … translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to any page … 43 … translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 1GB pages… 55 … translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 2M or 4M … 67 … translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 4K pages.… 112 … translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to any page … 124 … translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 1G pages.… 136 … translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 2M or 4M … 148 … translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 4K pages.… 265 … translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to any page … 277 … translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 1G pages.… [all …]
/Linux-v6.1/tools/perf/pmu-events/arch/x86/snowridgex/
D	memory.json	36 "BriefDescription": "Counts all code reads that were not supplied by the L3 cache.", 47 "BriefDescription": "Counts all code reads that were not supplied by the L3 cache.", 58 …"BriefDescription": "Counts modified writebacks from L1 cache and L2 cache that were not supplied … 69 …"BriefDescription": "Counts modified writebacks from L1 cache and L2 cache that were not supplied … 80 …ounts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the… 91 …ounts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the… 102 …cache hardware prefetches and software prefetches (except PREFETCHW) that were not supplied by the… 113 …cache hardware prefetches and software prefetches (except PREFETCHW) that were not supplied by the… 146 …ip (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the… 157 …ip (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the… [all …]
D	cache.json	344 "BriefDescription": "Counts the number of memory uops retired that were splits.", 380 "BriefDescription": "Counts all code reads that were supplied by the L3 cache.", 391 …"BriefDescription": "Counts all code reads that were supplied by the L3 cache where a snoop was se… 402 …"BriefDescription": "Counts all code reads that were supplied by the L3 cache where a snoop was se… 413 …"BriefDescription": "Counts all code reads that were supplied by the L3 cache where a snoop was se… 424 …"BriefDescription": "Counts all code reads that were supplied by the L3 cache where a snoop was se… 435 …"BriefDescription": "Counts all code reads that were supplied by the L3 cache where no snoop was n… 446 …"BriefDescription": "Counts modified writebacks from L1 cache and L2 cache that were supplied by t… 457 …ounts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 … 468 …ounts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 … [all …]
D	pipeline.json	366 …"BriefDescription": "Counts the total number of issue slots that were not consumed by the backend … 373 …were not consumed by the backend because allocation is stalled due to a mispredicted jump or a mac… 378 …"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the ba… 389 …"BriefDescription": "Counts the total number of issue slots that were not consumed by the backend … 400 …"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the ba… 422 …"BriefDescription": "Counts the total number of issue slots every cycle that were not consumed by … 432 …"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the ba… 443 …"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the ba… 454 …"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the ba… 465 …"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the ba… [all …]
D	other.json	148 "BriefDescription": "Counts all code reads that were supplied by DRAM.", 159 "BriefDescription": "Counts all code reads that were supplied by DRAM.", 214 …Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM.", 225 …Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM.", 247 … cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by DRAM.", 258 … cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by DRAM.", 335 …hip (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM.", 346 …hip (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM.", 401 … L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by DRAM.", 412 … L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by DRAM.", [all …]
D	virtual-memory.json	31 … translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to any page … 43 … translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 1GB pages… 55 … translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 2M or 4M … 67 … translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 4K pages.… 112 … translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to any page … 124 … translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 1G pages.… 136 … translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 2M or 4M … 148 … translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 4K pages.… 265 … translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to any page … 277 … translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 1G pages.… [all …]
/Linux-v6.1/tools/perf/pmu-events/arch/x86/icelakex/
D	other.json	127 …Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM.", 138 …ounts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM at… 149 …ounts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM on… 171 "BriefDescription": "Counts demand data reads that were supplied by DRAM.", 182 …"BriefDescription": "Counts demand data reads that were supplied by DRAM attached to this socket, … 193 …"BriefDescription": "Counts demand data reads that were supplied by PMM attached to this socket, u… 204 "BriefDescription": "Counts demand data reads that were supplied by PMM.", 215 …"BriefDescription": "Counts demand data reads that were supplied by DRAM attached to another socke… 226 …"BriefDescription": "Counts demand data reads that were supplied by PMM attached to another socket… 237 …"BriefDescription": "Counts demand data reads that were supplied by DRAM on a distant memory contr… [all …]
D	memory.json	155 …ounts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the… 166 …ounts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the… 177 …"BriefDescription": "Counts demand data reads that were not supplied by the local socket's L1, L2,… 188 …"BriefDescription": "Counts demand data reads that were not supplied by the local socket's L1, L2,… 199 …requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the… 210 … for exclusive ownership (PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 ca… 221 …a cache prefetch requests and software prefetches (except PREFETCHW) that were not supplied by the… 232 …a cache prefetch requests and software prefetches (except PREFETCHW) that were not supplied by the… 254 …"BriefDescription": "Counts hardware prefetches to the L3 only that were not supplied by the local… 265 …"BriefDescription": "Counts full cacheline writes (ItoM) that were not supplied by the local socke… [all …]
D	cache.json	402 …"BriefDescription": "Retired load instructions whose data sources were HitM responses from shared … 410 …"PublicDescription": "Counts retired load instructions whose data sources were HitM responses from… 439 …"BriefDescription": "Retired load instructions whose data sources were L3 hit and cross-core snoop… 447 …"PublicDescription": "Counts the retired load instructions whose data sources were L3 hit and cros… 452 …"BriefDescription": "Retired load instructions whose data sources were hits in L3 without snoops r… 460 …"PublicDescription": "Counts retired load instructions whose data sources were hits in L3 without … 465 …"BriefDescription": "Retired load instructions whose data sources were L3 and cross-core snoop hit… 473 …"PublicDescription": "Counts retired load instructions whose data sources were L3 and cross-core s… 659 …ruction fetches and L1 instruction cache prefetches that hit in the L3 or were snooped from anothe… 681 …uction cache prefetches that hit a modified line in a distant L3 Cache or were snooped from a dist… [all …]
/Linux-v6.1/Documentation/userspace-api/media/v4l/
D	hist-v4l2.rst	29 aliases ``O_NONCAP`` and ``O_NOIO`` were defined. Applications can set 40 struct ``video_standard`` and the color subcarrier fields were 59 module. The ``YUV422`` and ``YUV411`` planar image formats were added. 62 output devices were added. 110 Version 0.20 introduced a number of changes which were *not backward 115 1. Some typos in ``V4L2_FMT_FLAG`` symbols were fixed. struct v4l2_clip 137 4. All the different get- and set-format commands were swept into one 152 ``VIDIOC_S_PARM`` ioctls were merged with ``VIDIOC_G_OUTPARM`` and 159 6. Control enumeration was simplified, and two new control flags were 188 cause errors if it were being used for timestamping a multimedia [all …]
/Linux-v6.1/tools/perf/pmu-events/arch/x86/sapphirerapids/
D	other.json	35 …Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM.", 46 …ounts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM at… 57 …ounts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM on… 79 "BriefDescription": "Counts demand data reads that were supplied by DRAM.", 90 …"BriefDescription": "Counts demand data reads that were supplied by DRAM attached to this socket, … 101 …"BriefDescription": "Counts demand data reads that were supplied by DRAM attached to another socke… 112 …"BriefDescription": "Counts demand data reads that were supplied by PMM attached to another socket… 123 …"BriefDescription": "Counts demand data reads that were supplied by DRAM on a distant memory contr… 145 … requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM.", 156 …requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM at… [all …]
D	cache.json	153 …Description": "Counts all requests that were hit or true misses in L2 cache. True-miss excludes mi… 165 …ny type with true-miss in the L2 cache. True-miss excludes L2 misses that were merged with ongoing… 189 …e. These requests may hit or miss L2 cache. True-miss exclude misses that were merged with ongoing… 284 …d requests with true-miss in the L2 cache. True-miss excludes misses that were merged with ongoing… 307 …ny type with true-miss in the L2 cache. True-miss excludes L2 misses that were merged with ongoing… 319 …Description": "Counts all requests that were hit or true misses in L2 cache. True-miss excludes mi… 517 …"BriefDescription": "Retired load instructions whose data sources were HitM responses from shared … 525 …"PublicDescription": "Counts retired load instructions whose data sources were HitM responses from… 530 …"BriefDescription": "Retired load instructions whose data sources were L3 hit and cross-core snoop… 538 …"PublicDescription": "Counts the retired load instructions whose data sources were L3 hit and cros… [all …]
/Linux-v6.1/Documentation/networking/device_drivers/ethernet/altera/
D	altera_tse.rst	14 driver were built for a Cyclone(R) V SOC FPGA board, a Cyclone(R) V FPGA board, 26 Quartus toolchain. Quartus 13.1 and 14.0 were used to build the design that 201 statistic is a count of the number of packets received that were not addressed 205 statistic is a count of the number of packets received that were addressed to 209 statistic is a count of the number of packets received that were addressed to 218 statistic counts the number of packets transmitted that were not addressed to 222 statistic counts the number of packets transmitted that were addressed to a 226 statistic counts the number of packets transmitted that were addressed to a 250 This statistic counts the total number of packets received that were 64 octets 254 2819. This statistic counts the total number of packets received that were [all …]
/Linux-v6.1/Documentation/scheduler/
D	sched-nice-design.rst	8 Nice levels were always pretty weak under Linux and people continuously 14 units were driven by the HZ tick, so the smallest timeslice was 1/HZ. 17 much stronger than they were before in 2.4 (and people were happy about 48 this was long ago when hardware was weaker and caches were smaller, and 49 people were running number crunching apps at nice +19.) 83 nice levels were not 'punchy enough', so lots of people had to resort to 104 levels were changed to be "multiplicative" (or exponential) - that way
/Linux-v6.1/block/partitions/
D	Kconfig	`11 were partitioned under an operating system running on a different 32 were partitioned using the Cumana interface on Acorn machines. 45 were partitioned using the ICS interface on Acorn machines. 90 were partitioned on an Alpha machine. 97 were partitioned under AmigaOS. 104 were partitioned under the Atari OS. 119 were partitioned on a Macintosh. 183 were partitioned using Windows 2000's/XP's or Vista's Logical Disk 256 were partitioned using EFI GPT.`
/Linux-v6.1/tools/perf/pmu-events/arch/x86/goldmontplus/
D	virtual-memory.json	10 …ng SW prefetches) whose address translations missed in all TLB levels and were mapped to 1GB pages… 22 …ng SW prefetches) whose address translations missed in all TLB levels and were mapped to 2M or 4M … 34 …ng SW prefetches) whose address translations missed in all TLB levels and were mapped to 4K pages.… 58 …ue to demand data stores whose address translations missed in the TLB and were mapped to 1GB pages… 70 …ue to demand data stores whose address translations missed in the TLB and were mapped to 2M or 4M … 82 …ue to demand data stores whose address translations missed in the TLB and were mapped to 4K pages.… 130 …e to instruction fetches whose address translations missed in the TLB and were mapped to 1GB pages… 142 …e to instruction fetches whose address translations missed in the TLB and were mapped to 2M or 4M … 154 …e to instruction fetches whose address translations missed in the TLB and were mapped to 4K pages.…
/Linux-v6.1/Documentation/powerpc/
D	vcpudispatch_stats.rst	`68 statistics were enabled. 4126 of those dispatches were on the same 69 physical cpu as the last time. 2683 were on a different core, but within 70 the same chip, while 30 dispatches were on a different chip compared to 74 6821 dispatches on the vcpu's home node, while 18 dispatches were`
/Linux-v6.1/tools/perf/pmu-events/arch/x86/amdzen3/
D	core.json	23 "PublicDescription": "The number of retired branch instructions, that were mispredicted." 29 …"PublicDescription": "The number of taken branches that were retired. This includes all types of a… 35 "PublicDescription": "The number of retired taken branch instructions that were mispredicted." 59 …"PublicDescription": "The number of near returns retired that were not correctly predicted by the … 65 …"PublicDescription": "The number of indirect branches retired that were not correctly predicted. E… 112 …"PublicDescription": "The number of retired conditional branch instructions that were not correctl…
/Linux-v6.1/Documentation/networking/devlink/
D	devlink-trap.rst	91 * ``drop``: Trapped packets were dropped by the underlying device. Packets 94 * ``exception``: Trapped packets were not forwarded as intended by the 100 * ``control``: Trapped packets were trapped by the device because these are 160 is the port from which they were received 216 - Traps packets that should have been routed by the device, but were bigger 347 interface from which they were received. Such packets are routed by the 519 - Contains packet traps for packets that were dropped by the device during 522 - Contains packet traps for packets that were dropped by the device during 528 - Contains packet traps for packets that were dropped by the device due to 531 - Contains packet traps for packets that were dropped by the device during [all …]
/Linux-v6.1/arch/x86/include/asm/
D	olpc.h	`55 * order) were created: A1, B1, B2, B3, B4, C1. The A1 through B2 models 56 * were based on Geode GX CPUs, and models after that were based upon 57 * Geode LX CPUs. There were also some hand-assembled models floating`
/Linux-v6.1/tools/perf/pmu-events/arch/powerpc/power10/
D	memory.json	10 …:12]. If MMCR1[16\|17] is 0 (default), this count includes only lines that were reloaded to satisfy… 15 …:12]. If MMCR1[16\|17] is 0 (default), this count includes only lines that were reloaded to satisfy… 70 …:27]. If MMCR1[16\|17] is 0 (default), this count includes only lines that were reloaded to satisfy… 100 …:42]. If MMCR1[16\|17] is 0 (default), this count includes only lines that were reloaded to satisfy… 105 …:42]. If MMCR1[16\|17] is 0 (default), this count includes only lines that were reloaded to satisfy… 150 …:57]. If MMCR1[16\|17] is 0 (default), this count includes only lines that were reloaded to satisfy… 155 …:57]. If MMCR1[16\|17] is 0 (default), this count includes only lines that were reloaded to satisfy…

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