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/Linux-v5.15/drivers/media/platform/mtk-vpu/
Dmtk_vpu.c23 * VPU (video processor unit) is a tiny processor controlling video hardware
25 * VPU interfaces with other blocks by share memory and interrupt.
44 /* the size of share buffer between Host and VPU */
68 /* vpu inter-processor communication interrupt */
70 /* vpu idle state */
74 * enum vpu_fw_type - VPU firmware type
86 * struct vpu_mem - VPU extended program/data memory information
88 * @va: the kernel virtual memory address of VPU extended memory
89 * @pa: the physical memory address of VPU extended memory
98 * struct vpu_regs - VPU TCM and configuration registers
[all …]
Dmtk_vpu.h13 * DOC: VPU
15 * VPU (video processor unit) is a tiny processor controlling video hardware
17 * VPU interfaces with other blocks by share memory and interrupt.
27 * @IPI_VPU_INIT: The interrupt from vpu is to notfiy kernel
28 * VPU initialization completed.
29 * IPI_VPU_INIT is sent from VPU when firmware is
31 * command to VPU.
33 * to VPU to trigger the interrupt.
34 * @IPI_VDEC_H264: The interrupt from vpu is to notify kernel to
42 * @IPI_VDEC_VP9: The interrupt from vpu is to notify kernel to
[all …]
/Linux-v5.15/drivers/media/platform/mtk-vcodec/
Dvdec_vpu_if.c15 struct vdec_vpu_inst *vpu = (struct vdec_vpu_inst *) in handle_init_ack_msg() local
18 mtk_vcodec_debug(vpu, "+ ap_inst_addr = 0x%llx", msg->ap_inst_addr); in handle_init_ack_msg()
20 /* mapping VPU address to kernel virtual address */ in handle_init_ack_msg()
21 /* the content in vsi is initialized to 0 in VPU */ in handle_init_ack_msg()
22 vpu->vsi = mtk_vcodec_fw_map_dm_addr(vpu->ctx->dev->fw_handler, in handle_init_ack_msg()
24 vpu->inst_addr = msg->vpu_inst_addr; in handle_init_ack_msg()
26 mtk_vcodec_debug(vpu, "- vpu_inst_addr = 0x%x", vpu->inst_addr); in handle_init_ack_msg()
30 * vpu_dec_ipi_handler - Handler for VPU ipi message.
37 * from VPU.
42 struct vdec_vpu_inst *vpu = (struct vdec_vpu_inst *) in vpu_dec_ipi_handler() local
[all …]
Dvenc_vpu_if.c12 static void handle_enc_init_msg(struct venc_vpu_inst *vpu, const void *data) in handle_enc_init_msg() argument
16 vpu->inst_addr = msg->vpu_inst_addr; in handle_enc_init_msg()
17 vpu->vsi = mtk_vcodec_fw_map_dm_addr(vpu->ctx->dev->fw_handler, in handle_enc_init_msg()
21 if (vpu->ctx->dev->venc_pdata->chip == MTK_MT8173) in handle_enc_init_msg()
25 mtk_vcodec_debug(vpu, "firmware version: 0x%x\n", in handle_enc_init_msg()
31 mtk_vcodec_err(vpu, "unhandled firmware version 0x%x\n", in handle_enc_init_msg()
33 vpu->failure = 1; in handle_enc_init_msg()
38 static void handle_enc_encode_msg(struct venc_vpu_inst *vpu, const void *data) in handle_enc_encode_msg() argument
42 vpu->state = msg->state; in handle_enc_encode_msg()
43 vpu->bs_size = msg->bs_size; in handle_enc_encode_msg()
[all …]
Dvdec_vpu_if.h15 * struct vdec_vpu_inst - VPU instance for video codec
17 * @vsi : driver structure allocated by VPU side and shared to AP side
19 * @failure : VPU execution result status, 0: success, others: fail
20 * @inst_addr : VPU decoder instance address
21 * @signaled : 1 - Host has received ack message from VPU, 0 - not received
23 * @dev : platform device of VPU
24 * @wq : wait queue to wait VPU message ack
39 * vpu_dec_init - init decoder instance and allocate required resource in VPU.
41 * @vpu: instance for vdec_vpu_inst
43 int vpu_dec_init(struct vdec_vpu_inst *vpu);
[all …]
Dvenc_ipi_msg.h16 * enum venc_ipi_msg_id - message id between AP and VPU
18 * @AP_IPIMSG_ENC_XXX: AP to VPU cmd message id
19 * @VPU_IPIMSG_ENC_XXX_DONE: VPU ack AP cmd message id
34 * struct venc_ap_ipi_msg_init - AP to VPU init cmd structure
36 * @reserved: reserved for future use. vpu is running in 32bit. Without
38 * will be different between kernel and vpu
49 * struct venc_ap_ipi_msg_set_param - AP to VPU set_param cmd structure
51 * @vpu_inst_addr: VPU encoder instance addr
71 * struct venc_ap_ipi_msg_enc - AP to VPU enc cmd structure
73 * @vpu_inst_addr: VPU encoder instance addr
[all …]
Dvenc_vpu_if.h14 * struct venc_vpu_inst - encoder VPU driver instance
15 * @wq_hd: wait queue used for vpu cmd trigger then wait vpu interrupt done
16 * @signaled: flag used for checking vpu interrupt done
17 * @failure: flag to show vpu cmd succeeds or not
21 * @inst_addr: VPU instance addr
22 * @vsi: driver structure allocated by VPU side and shared to AP side for
41 int vpu_enc_init(struct venc_vpu_inst *vpu);
42 int vpu_enc_set_param(struct venc_vpu_inst *vpu,
45 int vpu_enc_encode(struct venc_vpu_inst *vpu, unsigned int bs_mode,
50 int vpu_enc_deinit(struct venc_vpu_inst *vpu);
/Linux-v5.15/drivers/staging/media/hantro/
Dhantro_g2_hevc_dec.c3 * Hantro VPU HEVC codec driver
18 static inline void hantro_write_addr(struct hantro_dev *vpu, in hantro_write_addr() argument
22 vdpu_write(vpu, addr & 0xffffffff, offset); in hantro_write_addr()
27 struct hantro_dev *vpu = ctx->dev; in prepare_tile_info_buffer() local
42 hantro_reg_write(vpu, &g2_tile_e, tiles_enabled); in prepare_tile_info_buffer()
60 hantro_reg_write(vpu, &g2_num_tile_rows, num_tile_rows); in prepare_tile_info_buffer()
61 hantro_reg_write(vpu, &g2_num_tile_cols, num_tile_cols); in prepare_tile_info_buffer()
108 hantro_reg_write(vpu, &g2_num_tile_rows, 1); in prepare_tile_info_buffer()
109 hantro_reg_write(vpu, &g2_num_tile_cols, 1); in prepare_tile_info_buffer()
126 struct hantro_dev *vpu = ctx->dev; in set_params() local
[all …]
Dhantro_drv.c3 * Hantro VPU codec driver
31 #define DRIVER_NAME "hantro-vpu"
59 static void hantro_job_finish_no_pm(struct hantro_dev *vpu, in hantro_job_finish_no_pm() argument
80 static void hantro_job_finish(struct hantro_dev *vpu, in hantro_job_finish() argument
84 pm_runtime_mark_last_busy(vpu->dev); in hantro_job_finish()
85 pm_runtime_put_autosuspend(vpu->dev); in hantro_job_finish()
87 clk_bulk_disable(vpu->variant->num_clocks, vpu->clocks); in hantro_job_finish()
89 hantro_job_finish_no_pm(vpu, ctx, result); in hantro_job_finish()
92 void hantro_irq_done(struct hantro_dev *vpu, in hantro_irq_done() argument
96 v4l2_m2m_get_curr_priv(vpu->m2m_dev); in hantro_irq_done()
[all …]
Dimx8m_vpu_hw.c3 * Hantro VPU codec driver
28 static void imx8m_soft_reset(struct hantro_dev *vpu, u32 reset_bits) in imx8m_soft_reset() argument
33 val = readl(vpu->ctrl_base + CTRL_SOFT_RESET); in imx8m_soft_reset()
35 writel(val, vpu->ctrl_base + CTRL_SOFT_RESET); in imx8m_soft_reset()
40 val = readl(vpu->ctrl_base + CTRL_SOFT_RESET); in imx8m_soft_reset()
42 writel(val, vpu->ctrl_base + CTRL_SOFT_RESET); in imx8m_soft_reset()
45 static void imx8m_clk_enable(struct hantro_dev *vpu, u32 clock_bits) in imx8m_clk_enable() argument
49 val = readl(vpu->ctrl_base + CTRL_CLOCK_ENABLE); in imx8m_clk_enable()
51 writel(val, vpu->ctrl_base + CTRL_CLOCK_ENABLE); in imx8m_clk_enable()
54 static int imx8mq_runtime_resume(struct hantro_dev *vpu) in imx8mq_runtime_resume() argument
[all …]
Dhantro_postproc.c15 #define HANTRO_PP_REG_WRITE(vpu, reg_name, val) \ argument
17 hantro_reg_write(vpu, \
18 &(vpu)->variant->postproc_regs->reg_name, \
22 #define HANTRO_PP_REG_WRITE_S(vpu, reg_name, val) \ argument
24 hantro_reg_write_s(vpu, \
25 &(vpu)->variant->postproc_regs->reg_name, \
56 struct hantro_dev *vpu = ctx->dev; in hantro_needs_postproc() local
61 if (!vpu->variant->postproc_fmts) in hantro_needs_postproc()
69 struct hantro_dev *vpu = ctx->dev; in hantro_postproc_enable() local
74 if (!vpu->variant->postproc_regs) in hantro_postproc_enable()
[all …]
Drockchip_vpu2_hw_jpeg_enc.c3 * Hantro VPU codec driver
9 * The VPU JPEG encoder produces JPEG baseline sequential format.
35 static void rockchip_vpu2_set_src_img_ctrl(struct hantro_dev *vpu, in rockchip_vpu2_set_src_img_ctrl() argument
46 vepu_write_relaxed(vpu, reg, VEPU_REG_INPUT_LUMA_INFO); in rockchip_vpu2_set_src_img_ctrl()
56 vepu_write_relaxed(vpu, reg, VEPU_REG_ENC_OVER_FILL_STRM_OFFSET); in rockchip_vpu2_set_src_img_ctrl()
59 vepu_write_relaxed(vpu, reg, VEPU_REG_ENC_CTRL1); in rockchip_vpu2_set_src_img_ctrl()
62 static void rockchip_vpu2_jpeg_enc_set_buffers(struct hantro_dev *vpu, in rockchip_vpu2_jpeg_enc_set_buffers() argument
71 vepu_write_relaxed(vpu, ctx->jpeg_enc.bounce_buffer.dma, in rockchip_vpu2_jpeg_enc_set_buffers()
73 vepu_write_relaxed(vpu, ctx->jpeg_enc.bounce_buffer.size, in rockchip_vpu2_jpeg_enc_set_buffers()
78 vepu_write_relaxed(vpu, src[0], VEPU_REG_ADDR_IN_PLANE_0); in rockchip_vpu2_jpeg_enc_set_buffers()
[all …]
Dhantro_h1_jpeg_enc.c3 * Hantro VPU codec driver
18 static void hantro_h1_set_src_img_ctrl(struct hantro_dev *vpu, in hantro_h1_set_src_img_ctrl() argument
28 vepu_write_relaxed(vpu, reg, H1_REG_IN_IMG_CTRL); in hantro_h1_set_src_img_ctrl()
31 static void hantro_h1_jpeg_enc_set_buffers(struct hantro_dev *vpu, in hantro_h1_jpeg_enc_set_buffers() argument
40 vepu_write_relaxed(vpu, ctx->jpeg_enc.bounce_buffer.dma, in hantro_h1_jpeg_enc_set_buffers()
42 vepu_write_relaxed(vpu, ctx->jpeg_enc.bounce_buffer.size, in hantro_h1_jpeg_enc_set_buffers()
48 vepu_write_relaxed(vpu, src[0], H1_REG_ADDR_IN_PLANE_0); in hantro_h1_jpeg_enc_set_buffers()
52 vepu_write_relaxed(vpu, src[0], H1_REG_ADDR_IN_PLANE_0); in hantro_h1_jpeg_enc_set_buffers()
53 vepu_write_relaxed(vpu, src[1], H1_REG_ADDR_IN_PLANE_1); in hantro_h1_jpeg_enc_set_buffers()
58 vepu_write_relaxed(vpu, src[0], H1_REG_ADDR_IN_PLANE_0); in hantro_h1_jpeg_enc_set_buffers()
[all …]
Drockchip_vpu_hw.c3 * Hantro VPU codec driver
208 struct hantro_dev *vpu = dev_id; in rockchip_vpu1_vepu_irq() local
212 status = vepu_read(vpu, H1_REG_INTERRUPT); in rockchip_vpu1_vepu_irq()
216 vepu_write(vpu, 0, H1_REG_INTERRUPT); in rockchip_vpu1_vepu_irq()
217 vepu_write(vpu, 0, H1_REG_AXI_CTRL); in rockchip_vpu1_vepu_irq()
219 hantro_irq_done(vpu, state); in rockchip_vpu1_vepu_irq()
226 struct hantro_dev *vpu = dev_id; in rockchip_vpu2_vdpu_irq() local
230 status = vdpu_read(vpu, VDPU_REG_INTERRUPT); in rockchip_vpu2_vdpu_irq()
234 vdpu_write(vpu, 0, VDPU_REG_INTERRUPT); in rockchip_vpu2_vdpu_irq()
235 vdpu_write(vpu, 0, VDPU_REG_AXI_CTRL); in rockchip_vpu2_vdpu_irq()
[all …]
Drockchip_vpu2_hw_vp8_dec.c3 * Rockchip VPU codec vp8 decode driver
280 struct hantro_dev *vpu = ctx->dev; in cfg_lf() local
285 hantro_reg_write(vpu, &vp8_dec_lf_level[0], lf->level); in cfg_lf()
291 hantro_reg_write(vpu, &vp8_dec_lf_level[i], lf_level); in cfg_lf()
295 hantro_reg_write(vpu, &vp8_dec_lf_level[i], in cfg_lf()
302 vdpu_write_relaxed(vpu, reg, VDPU_REG_FILTER_MB_ADJ); in cfg_lf()
306 hantro_reg_write(vpu, &vp8_dec_mb_adj[i], in cfg_lf()
308 hantro_reg_write(vpu, &vp8_dec_ref_adj[i], in cfg_lf()
319 struct hantro_dev *vpu = ctx->dev; in cfg_qp() local
323 hantro_reg_write(vpu, &vp8_dec_quant[0], q->y_ac_qi); in cfg_qp()
[all …]
Dhantro_g1_h264_dec.c3 * Rockchip RK3288 VPU codec driver
28 struct hantro_dev *vpu = ctx->dev; in set_params() local
49 vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL0); in set_params()
55 vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL1); in set_params()
65 vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL2); in set_params()
71 vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL3); in set_params()
85 vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL4); in set_params()
100 vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL5); in set_params()
107 vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL6); in set_params()
110 vdpu_write_relaxed(vpu, 0, G1_REG_ERR_CONC); in set_params()
[all …]
Drockchip_vpu2_hw_mpeg2_dec.c3 * Hantro VPU codec driver
83 rockchip_vpu2_mpeg2_dec_set_quantisation(struct hantro_dev *vpu, in rockchip_vpu2_mpeg2_dec_set_quantisation() argument
90 vdpu_write_relaxed(vpu, ctx->mpeg2_dec.qtable.dma, VDPU_REG_QTABLE_BASE); in rockchip_vpu2_mpeg2_dec_set_quantisation()
94 rockchip_vpu2_mpeg2_dec_set_buffers(struct hantro_dev *vpu, in rockchip_vpu2_mpeg2_dec_set_buffers() argument
114 vdpu_write_relaxed(vpu, addr, VDPU_REG_RLC_VLC_BASE); in rockchip_vpu2_mpeg2_dec_set_buffers()
122 vdpu_write_relaxed(vpu, addr, VDPU_REG_DEC_OUT_BASE); in rockchip_vpu2_mpeg2_dec_set_buffers()
136 vdpu_write_relaxed(vpu, forward_addr, VDPU_REG_REFER0_BASE); in rockchip_vpu2_mpeg2_dec_set_buffers()
137 vdpu_write_relaxed(vpu, forward_addr, VDPU_REG_REFER1_BASE); in rockchip_vpu2_mpeg2_dec_set_buffers()
139 vdpu_write_relaxed(vpu, forward_addr, VDPU_REG_REFER0_BASE); in rockchip_vpu2_mpeg2_dec_set_buffers()
140 vdpu_write_relaxed(vpu, current_addr, VDPU_REG_REFER1_BASE); in rockchip_vpu2_mpeg2_dec_set_buffers()
[all …]
Dhantro_g1_vp8_dec.c139 struct hantro_dev *vpu = ctx->dev; in cfg_lf() local
144 hantro_reg_write(vpu, &vp8_dec_lf_level[0], lf->level); in cfg_lf()
150 hantro_reg_write(vpu, &vp8_dec_lf_level[i], lf_level); in cfg_lf()
154 hantro_reg_write(vpu, &vp8_dec_lf_level[i], in cfg_lf()
161 vdpu_write_relaxed(vpu, reg, G1_REG_REF_PIC(0)); in cfg_lf()
165 hantro_reg_write(vpu, &vp8_dec_mb_adj[i], in cfg_lf()
167 hantro_reg_write(vpu, &vp8_dec_ref_adj[i], in cfg_lf()
181 struct hantro_dev *vpu = ctx->dev; in cfg_qp() local
185 hantro_reg_write(vpu, &vp8_dec_quant[0], q->y_ac_qi); in cfg_qp()
191 hantro_reg_write(vpu, &vp8_dec_quant[i], quant); in cfg_qp()
[all …]
Dhantro.h3 * Hantro VPU codec driver
52 * struct hantro_variant - information about VPU hardware variant
54 * @enc_offset: Offset from VPU base to encoder registers.
55 * @dec_offset: Offset from VPU base to decoder registers.
85 int (*init)(struct hantro_dev *vpu);
86 int (*runtime_resume)(struct hantro_dev *vpu);
125 * struct hantro_func - Hantro VPU functionality
166 * @pdev: Pointer to VPU platform device.
170 * @reg_bases: Mapped addresses of VPU registers.
171 * @enc_base: Mapped address of VPU encoder register for convenience.
[all …]
Dhantro_g1.c3 * Hantro VPU codec driver
16 struct hantro_dev *vpu = dev_id; in hantro_g1_irq() local
20 status = vdpu_read(vpu, G1_REG_INTERRUPT); in hantro_g1_irq()
24 vdpu_write(vpu, 0, G1_REG_INTERRUPT); in hantro_g1_irq()
25 vdpu_write(vpu, G1_REG_CONFIG_DEC_CLK_GATE_E, G1_REG_CONFIG); in hantro_g1_irq()
27 hantro_irq_done(vpu, state); in hantro_g1_irq()
34 struct hantro_dev *vpu = ctx->dev; in hantro_g1_reset() local
36 vdpu_write(vpu, G1_REG_INTERRUPT_DEC_IRQ_DIS, G1_REG_INTERRUPT); in hantro_g1_reset()
37 vdpu_write(vpu, G1_REG_CONFIG_DEC_CLK_GATE_E, G1_REG_CONFIG); in hantro_g1_reset()
38 vdpu_write(vpu, 1, G1_REG_SOFT_RESET); in hantro_g1_reset()
Dhantro_g1_mpeg2_dec.c3 * Hantro VPU codec driver
81 hantro_g1_mpeg2_dec_set_quantisation(struct hantro_dev *vpu, in hantro_g1_mpeg2_dec_set_quantisation() argument
88 vdpu_write_relaxed(vpu, ctx->mpeg2_dec.qtable.dma, G1_REG_QTABLE_BASE); in hantro_g1_mpeg2_dec_set_quantisation()
92 hantro_g1_mpeg2_dec_set_buffers(struct hantro_dev *vpu, struct hantro_ctx *ctx, in hantro_g1_mpeg2_dec_set_buffers() argument
111 vdpu_write_relaxed(vpu, addr, G1_REG_RLC_VLC_BASE); in hantro_g1_mpeg2_dec_set_buffers()
119 vdpu_write_relaxed(vpu, addr, G1_REG_DEC_OUT_BASE); in hantro_g1_mpeg2_dec_set_buffers()
133 vdpu_write_relaxed(vpu, forward_addr, G1_REG_REFER0_BASE); in hantro_g1_mpeg2_dec_set_buffers()
134 vdpu_write_relaxed(vpu, forward_addr, G1_REG_REFER1_BASE); in hantro_g1_mpeg2_dec_set_buffers()
136 vdpu_write_relaxed(vpu, forward_addr, G1_REG_REFER0_BASE); in hantro_g1_mpeg2_dec_set_buffers()
137 vdpu_write_relaxed(vpu, current_addr, G1_REG_REFER1_BASE); in hantro_g1_mpeg2_dec_set_buffers()
[all …]
/Linux-v5.15/drivers/remoteproc/
Dingenic_rproc.c53 * struct vpu - Ingenic VPU remoteproc private structure
55 * @clks: pointers to the VPU and AUX clocks
61 struct vpu { struct
71 struct vpu *vpu = rproc->priv; in ingenic_rproc_prepare() argument
75 ret = clk_bulk_prepare_enable(ARRAY_SIZE(vpu->clks), vpu->clks); in ingenic_rproc_prepare()
77 dev_err(vpu->dev, "Unable to start clocks: %d\n", ret); in ingenic_rproc_prepare()
84 struct vpu *vpu = rproc->priv; in ingenic_rproc_unprepare() local
86 clk_bulk_disable_unprepare(ARRAY_SIZE(vpu->clks), vpu->clks); in ingenic_rproc_unprepare()
93 struct vpu *vpu = rproc->priv; in ingenic_rproc_start() local
96 enable_irq(vpu->irq); in ingenic_rproc_start()
[all …]
/Linux-v5.15/drivers/media/platform/mtk-mdp/
Dmtk_mdp_vpu.c13 static inline struct mtk_mdp_ctx *vpu_to_ctx(struct mtk_mdp_vpu *vpu) in vpu_to_ctx() argument
15 return container_of(vpu, struct mtk_mdp_ctx, vpu); in vpu_to_ctx()
20 struct mtk_mdp_vpu *vpu = (struct mtk_mdp_vpu *) in mtk_mdp_vpu_handle_init_ack() local
23 /* mapping VPU address to kernel virtual address */ in mtk_mdp_vpu_handle_init_ack()
24 vpu->vsi = (struct mdp_process_vsi *) in mtk_mdp_vpu_handle_init_ack()
25 vpu_mapping_dm_addr(vpu->pdev, msg->vpu_inst_addr); in mtk_mdp_vpu_handle_init_ack()
26 vpu->inst_addr = msg->vpu_inst_addr; in mtk_mdp_vpu_handle_init_ack()
34 struct mtk_mdp_vpu *vpu = (struct mtk_mdp_vpu *) in mtk_mdp_vpu_ipi_handler() local
38 vpu->failure = msg->status; in mtk_mdp_vpu_ipi_handler()
39 if (!vpu->failure) { in mtk_mdp_vpu_ipi_handler()
[all …]
/Linux-v5.15/Documentation/devicetree/bindings/media/
Drockchip-vpu.yaml5 $id: "http://devicetree.org/schemas/media/rockchip-vpu.yaml#"
8 title: Hantro G1 VPU codecs implemented on Rockchip SoCs
20 - rockchip,rk3036-vpu
21 - rockchip,rk3066-vpu
22 - rockchip,rk3288-vpu
23 - rockchip,rk3328-vpu
24 - rockchip,rk3399-vpu
25 - rockchip,px30-vpu
27 - const: rockchip,rk3188-vpu
28 - const: rockchip,rk3066-vpu
[all …]
/Linux-v5.15/drivers/media/platform/mtk-vcodec/vdec/
Dvdec_vp9_if.c29 * struct vp9_dram_buf - contains buffer info for vpu
45 * @reserved : reserved field used by vpu
67 * @reserved : reserved field used by vpu
88 * struct vdec_vp9_vsi - shared buffer between host and VPU firmware
90 * VPU-W/R: VPU is write/reader on this item
91 * @sf_bs_buf : super frame backup buffer (AP-W, VPU-R)
93 * (AP-R/W, VPU-R/W)
94 * @sf_next_ref_fb_idx : next available super frame (AP-W, VPU-R)
95 * @sf_frm_cnt : super frame count, filled by vpu (AP-R, VPU-W)
96 * @sf_frm_offset : super frame offset, filled by vpu (AP-R, VPU-W)
[all …]

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