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/Linux-v6.1/drivers/pci/controller/
Dpcie-rockchip-host.c1 // SPDX-License-Identifier: GPL-2.0+
7 * Author: Shawn Lin <shawn.lin@rock-chips.com>
8 * Wenrui Li <wenrui.li@rock-chips.com>
40 #include "pcie-rockchip.h"
79 if (pci_is_root_bus(bus) || pci_is_root_bus(bus->parent)) in rockchip_pcie_valid_device()
90 if (rockchip->legacy_phy) in rockchip_pcie_lane_map()
91 return GENMASK(MAX_LANE_NUM - 1, 0); in rockchip_pcie_lane_map()
96 /* The link may be using a reverse-indexed mapping. */ in rockchip_pcie_lane_map()
108 addr = rockchip->apb_base + PCIE_RC_CONFIG_NORMAL_BASE + where; in rockchip_pcie_rd_own_conf()
135 addr = rockchip->apb_base + PCIE_RC_CONFIG_NORMAL_BASE + offset; in rockchip_pcie_wr_own_conf()
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Dpcie-rockchip.h1 /* SPDX-License-Identifier: GPL-2.0+ */
7 * Author: Shawn Lin <shawn.lin@rock-chips.com>
16 #include <linux/pci-ecam.h>
190 #define RC_REGION_0_PASS_BITS (25 - 1)
272 void __iomem *reg_base; /* DT axi-base */
273 void __iomem *apb_base; /* DT apb-base */
287 struct regulator *vpcie12v; /* 12V power supply */
288 struct regulator *vpcie3v3; /* 3.3V power supply */ member
289 struct regulator *vpcie1v8; /* 1.8V power supply */
290 struct regulator *vpcie0v9; /* 0.9V power supply */
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Dpcie-brcmstb.c1 // SPDX-License-Identifier: GPL-2.0+
2 /* Copyright (C) 2009 - 2019 Broadcom */
25 #include <linux/pci-ecam.h>
36 /* BRCM_PCIE_CAP_REGS - Offset for the mandatory capability config regs */
149 #define BRCM_INT_PCI_MSI_MASK GENMASK(BRCM_INT_PCI_MSI_NR - 1, 0)
151 32 - BRCM_INT_PCI_MSI_LEGACY_NR)
178 #define IDX_ADDR(pcie) (pcie->reg_offsets[EXT_CFG_INDEX])
179 #define DATA_ADDR(pcie) (pcie->reg_offsets[EXT_CFG_DATA])
180 #define PCIE_RGR1_SW_INIT_1(pcie) (pcie->reg_offsets[RGR1_SW_INIT_1])
270 return pcie->type == BCM7435 || pcie->type == BCM7425; in is_bmips()
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/Linux-v6.1/arch/arm64/boot/dts/rockchip/
Drk3399-roc-pc-mezzanine.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2017 T-Chip Intelligent Technology Co., Ltd
7 /dts-v1/;
8 #include "rk3399-roc-pc.dtsi"
11 model = "Firefly ROC-RK3399-PC Mezzanine Board";
12 compatible = "firefly,roc-rk3399-pc-mezzanine", "rockchip,rk3399";
19 poe_12v: poe-12v {
20 compatible = "regulator-fixed";
21 regulator-name = "poe_12v";
22 regulator-always-on;
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Drk3399-nanopc-t4.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * FriendlyElec NanoPC-T4 board device tree source
11 /dts-v1/;
12 #include "rk3399-nanopi4.dtsi"
15 model = "FriendlyElec NanoPC-T4";
16 compatible = "friendlyarm,nanopc-t4", "rockchip,rk3399";
18 vcc12v0_sys: vcc12v0-sys {
19 compatible = "regulator-fixed";
20 regulator-always-on;
21 regulator-boot-on;
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Drk3399-nanopi-r4s.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * FriendlyElec NanoPC-T4 board device tree source
15 /dts-v1/;
16 #include "rk3399-nanopi4.dtsi"
20 compatible = "friendlyarm,nanopi-r4s", "rockchip,rk3399";
22 /delete-node/ display-subsystem;
24 gpio-leds {
25 pinctrl-0 = <&lan_led_pin>, <&sys_led_pin>, <&wan_led_pin>;
27 /delete-node/ led-0;
29 lan_led: led-lan {
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Drk3568-bpi-r2-pro.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Author: Frank Wunderlich <frank-w@public-files.de>
7 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/leds/common.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/soc/rockchip,vop2.h>
15 model = "Bananapi-R2 Pro (RK3568) DDR4 Board";
16 compatible = "rockchip,rk3568-bpi-r2pro", "rockchip,rk3568";
26 stdout-path = "serial2:1500000n8";
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Drk3399pro-vmarc-som.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/pinctrl/rockchip.h>
10 #include <dt-bindings/pwm/pwm.h>
13 compatible = "vamrs,rk3399pro-vmarc-som", "rockchip,rk3399pro";
20 vcc3v3_pcie: vcc-pcie-regulator {
21 compatible = "regulator-fixed";
22 enable-active-high;
24 pinctrl-names = "default";
25 pinctrl-0 = <&pcie_pwr>;
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Drk3399-rock960.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
9 #include "rk3399-opp.dtsi"
10 #include <dt-bindings/interrupt-controller/irq.h>
19 sdio_pwrseq: sdio-pwrseq {
20 compatible = "mmc-pwrseq-simple";
22 clock-names = "ext_clock";
23 pinctrl-names = "default";
24 pinctrl-0 = <&wifi_enable_h>;
25 reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
28 vcc12v_dcin: vcc12v-dcin {
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Drk3399-kobol-helios64.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
13 /dts-v1/;
15 #include "rk3399-opp.dtsi"
29 avdd_0v9_s0: avdd-0v9-s0 {
30 compatible = "regulator-fixed";
31 regulator-name = "avdd_0v9_s0";
32 regulator-always-on;
33 regulator-boot-on;
34 regulator-min-microvolt = <900000>;
35 regulator-max-microvolt = <900000>;
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Drk3568-rock-3a.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 /dts-v1/;
4 #include <dt-bindings/gpio/gpio.h>
5 #include <dt-bindings/leds/common.h>
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include <dt-bindings/soc/rockchip,vop2.h>
21 stdout-path = "serial2:1500000n8";
24 hdmi-con {
25 compatible = "hdmi-connector";
30 remote-endpoint = <&hdmi_out_con>;
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Drk3566-quartz64-b.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 /dts-v1/;
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include <dt-bindings/soc/rockchip,vop2.h>
11 model = "Pine64 RK3566 Quartz64-B Board";
12 compatible = "pine64,quartz64-b", "rockchip,rk3566";
22 stdout-path = "serial2:1500000n8";
25 gmac1_clkin: external-gmac1-clock {
26 compatible = "fixed-clock";
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Drk3399-rock-pi-4.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
8 #include <dt-bindings/input/linux-event-codes.h>
9 #include <dt-bindings/leds/common.h>
10 #include <dt-bindings/pwm/pwm.h>
12 #include "rk3399-opp.dtsi"
21 stdout-path = "serial2:1500000n8";
24 clkin_gmac: external-gmac-clock {
25 compatible = "fixed-clock";
26 clock-frequency = <125000000>;
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Drk3566-quartz64-a.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 /dts-v1/;
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include <dt-bindings/soc/rockchip,vop2.h>
11 model = "Pine64 RK3566 Quartz64-A Board";
12 compatible = "pine64,quartz64-a", "rockchip,rk3566";
21 stdout-path = "serial2:1500000n8";
24 gmac1_clkin: external-gmac1-clock {
25 compatible = "fixed-clock";
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Drk3399-gru-scarlet.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Google Gru-scarlet board device tree source
8 #include "rk3399-gru.dtsi"
11 chassis-type = "tablet";
16 pp1250_s3: pp1250-s3 {
17 compatible = "regulator-fixed";
18 regulator-name = "pp1250_s3";
21 regulator-always-on;
22 regulator-boot-on;
23 regulator-min-microvolt = <1250000>;
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Drk3399-rockpro64.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include <dt-bindings/input/linux-event-codes.h>
8 #include <dt-bindings/pwm/pwm.h>
10 #include "rk3399-opp.dtsi"
20 stdout-path = "serial2:1500000n8";
25 compatible = "pwm-backlight";
26 brightness-levels = <0 4 8 16 32 64 128 255>;
27 default-brightness-level = <5>;
32 clkin_gmac: external-gmac-clock {
33 compatible = "fixed-clock";
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Drk3399-gru.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * Copyright 2016-2017 Google, Inc
8 #include <dt-bindings/input/input.h>
10 #include "rk3399-op1-opp.dtsi"
19 stdout-path = "serial2:115200n8";
28 * - Rails that only connect to the EC (or devices that the EC talks to)
30 * - Rails _are_ included if the rails go to the AP even if the AP
39 * - The EC controls the enable and the EC always enables a rail as
41 * - The rails are actually connected to each other by a jumper and
46 ppvar_sys: ppvar-sys {
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Drk3399-pinebook-pro.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 /dts-v1/;
9 #include <dt-bindings/input/gpio-keys.h>
10 #include <dt-bindings/input/linux-event-codes.h>
11 #include <dt-bindings/pwm/pwm.h>
12 #include <dt-bindings/usb/pd.h>
13 #include <dt-bindings/leds/common.h>
15 #include "rk3399-opp.dtsi"
19 compatible = "pine64,pinebook-pro", "rockchip,rk3399";
20 chassis-type = "laptop";
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/pci/
Dnvidia,tegra194-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/nvidia,tegra194-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Vidya Sagar <vidyas@nvidia.com>
16 inherits all the common properties defined in snps,dw-pcie.yaml. Some of
20 See nvidia,tegra194-pcie-ep.yaml for details on the Endpoint mode device
26 - nvidia,tegra194-pcie
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Drockchip-pcie-host.txt4 - #address-cells: Address representation for root ports, set to <3>
5 - #size-cells: Size representation for root ports, set to <2>
6 - #interrupt-cells: specifies the number of cells needed to encode an
8 - compatible: Should contain "rockchip,rk3399-pcie"
9 - reg: Two register ranges as listed in the reg-names property
10 - reg-names: Must include the following names
11 - "axi-base"
12 - "apb-base"
13 - clocks: Must contain an entry for each entry in clock-names.
14 See ../clocks/clock-bindings.txt for details.
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Drockchip-dw-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/rockchip-dw-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shawn Lin <shawn.lin@rock-chips.com>
11 - Simon Xue <xxm@rock-chips.com>
12 - Heiko Stuebner <heiko@sntech.de>
17 designware-pcie.txt.
20 - $ref: /schemas/pci/pci-bus.yaml#
25 - const: rockchip,rk3568-pcie
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Dbrcm,stb-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/brcm,stb-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
15 - enum:
16 - brcm,bcm2711-pcie # The Raspberry Pi 4
17 - brcm,bcm4908-pcie
18 - brcm,bcm7211-pcie # Broadcom STB version of RPi4
19 - brcm,bcm7278-pcie # Broadcom 7278 Arm
[all …]
/Linux-v6.1/arch/arm64/boot/dts/nvidia/
Dtegra194-p2972-0000.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/linux-event-codes.h>
5 #include <dt-bindings/input/gpio-keys.h>
7 #include "tegra194-p2888.dtsi"
11 compatible = "nvidia,p2972-0000", "nvidia,tegra194";
17 dma-controller@2930000 {
21 interrupt-controller@2a40000 {
29 #address-cells = <1>;
30 #size-cells = <0>;
[all …]
Dtegra234-p3737-0000+p3701-0000.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/linux-event-codes.h>
5 #include <dt-bindings/input/gpio-keys.h>
7 #include "tegra234-p3701-0000.dtsi"
8 #include "tegra234-p3737-0000.dtsi"
12 compatible = "nvidia,p3737-0000+p3701-0000", "nvidia,p3701-0000", "nvidia,tegra234";
28 #address-cells = <1>;
29 #size-cells = <0>;
35 remote-endpoint = <&admaif0>;
[all …]
/Linux-v6.1/drivers/pci/controller/dwc/
Dpcie-tegra194.c1 // SPDX-License-Identifier: GPL-2.0+
7 * Copyright (C) 2019-2022 NVIDIA Corporation.
35 #include "pcie-designware.h"
37 #include <soc/tegra/bpmp-abi.h>
300 writel_relaxed(value, pcie->appl_base + reg); in appl_writel()
305 return readl_relaxed(pcie->appl_base + reg); in appl_readl()
320 * NOTE:- Since this scenario is uncommon and link as such is not in apply_bad_link_workaround()
322 * transitioning to Gen-2 speed in apply_bad_link_workaround()
324 val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA); in apply_bad_link_workaround()
328 if (pcie->init_link_width > current_link_width) { in apply_bad_link_workaround()
[all …]