Searched +full:versal +full:- +full:cpm +full:- +full:host +full:- +full:1 (Results 1 – 3 of 3) sorted by relevance
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/pci/xilinx-versal-cpm.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: CPM Host Controller device tree for Xilinx Versal SoCs10 - Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>13 - $ref: /schemas/pci/pci-bus.yaml#17 const: xlnx,versal-cpm-host-1.0021 - description: Configuration space region and bridge registers.22 - description: CPM system level control and status registers.[all …]
1 # SPDX-License-Identifier: GPL-2.021 Add support for Aardvark 64bit PCIe Host Controller. This46 Say Y here if you want support for the PCIe host controller found50 bool "Renesas R-Car Gen2 Internal PCI controller"54 Say Y here if you want internal PCI support on R-Car Gen2 SoC.56 built-in EHCI/OHCI host controller present on each one.59 bool "Renesas R-Car PCIe controller"64 Say Y here if you want PCIe controller support on R-Car SoCs.68 bool "Renesas R-Car PCIe host controller"73 Say Y here if you want PCIe controller support on R-Car SoCs in host[all …]
1 // SPDX-License-Identifier: GPL-2.0+3 * PCIe host controller driver for Xilinx Versal CPM DMA Bridge5 * (C) Copyright 2019 - 2020, Xilinx, Inc.22 #include <linux/pci-ecam.h>36 #define XILINX_CPM_PCIE_MISC_IR_LOCAL BIT(1)102 * struct xilinx_cpm_pcie_port - PCIe port information104 * @cpm_base: CPM System Level Control and Status Register(SLCR) Base107 * @cpm_domain: CPM IRQ domain pointer127 return readl_relaxed(port->reg_base + reg); in pcie_read()133 writel_relaxed(val, port->reg_base + reg); in pcie_write()[all …]
