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/Linux-v5.15/Documentation/devicetree/bindings/regulator/
Dqcom,rpmh-regulator.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/regulator/qcom,rpmh-regulator.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - David Collins <collinsd@codeaurora.org>
13 rpmh-regulator devices support PMIC regulator management via the Voltage
21 It is used for clock buffers, low-voltage switches, and LDO/SMPS regulators
36 For PM6150, smps1 - smps5, ldo1 - ldo19
37 For PM6150L, smps1 - smps8, ldo1 - ldo11, bob
38 For PM7325, smps1 - smps8, ldo1 - ldo19
[all …]
/Linux-v5.15/arch/arm64/boot/dts/qcom/
Dsm8150-sony-xperia-kumano.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
6 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
15 /delete-node/ &cdsp_mem;
16 /delete-node/ &gpu_mem;
17 /delete-node/ &ipa_fw_mem;
18 /delete-node/ &ipa_gsi_mem;
19 /delete-node/ &mpss_mem;
20 /delete-node/ &slpi_mem;
[all …]
Dsm8150-mtp.dts1 // SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
7 /dts-v1/;
9 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
10 #include <dt-bindings/gpio/gpio.h>
18 compatible = "qcom,sm8150-mtp", "qcom,sm8150";
25 stdout-path = "serial0:115200n8";
28 vph_pwr: vph-pwr-regulator {
29 compatible = "regulator-fixed";
30 regulator-name = "vph_pwr";
[all …]
Dsm8150-hdk.dts1 // SPDX-License-Identifier: BSD-3-Clause
6 /dts-v1/;
8 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
9 #include <dt-bindings/gpio/gpio.h>
17 compatible = "qcom,sm8150-hdk", "qcom,sm8150";
24 stdout-path = "serial0:115200n8";
27 vph_pwr: vph-pwr-regulator {
28 compatible = "regulator-fixed";
29 regulator-name = "vph_pwr";
30 regulator-min-microvolt = <3700000>;
[all …]
Dsm8150-microsoft-surface-duo.dts1 // SPDX-License-Identifier: BSD-3-Clause
6 /dts-v1/;
8 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
9 #include <dt-bindings/gpio/gpio.h>
17 compatible = "microsoft,surface-duo", "qcom,sm8150";
24 stdout-path = "serial0:115200n8";
27 vph_pwr: vph-pwr-regulator {
28 compatible = "regulator-fixed";
29 regulator-name = "vph_pwr";
30 regulator-min-microvolt = <3700000>;
[all …]
Dsm8250-sony-xperia-edo.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
13 /delete-node/ &adsp_mem;
14 /delete-node/ &spss_mem;
15 /delete-node/ &cdsp_secure_heap;
18 qcom,msm-id = <356 0x20001>; /* SM8250 v2.1 */
19 qcom,board-id = <0x10008 0>;
22 #address-cells = <2>;
23 #size-cells = <2>;
27 compatible = "simple-framebuffer";
[all …]
/Linux-v5.15/arch/arm/boot/dts/
Dtegra30-colibri-eval-v3.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/input.h>
5 #include "tegra30-colibri.dtsi"
9 compatible = "toradex,colibri_t30-eval-v3", "toradex,colibri_t30",
22 stdout-path = "serial0:115200n8";
27 rgb {
35 hdmi-supply = <&reg_5v0>;
39 /* Colibri UART-A */
44 /* Colibri UART-C */
[all …]
Dtegra20-colibri-eval-v3.dts1 // SPDX-License-Identifier: GPL-2.0 OR MIT
2 /dts-v1/;
4 #include <dt-bindings/input/input.h>
5 #include "tegra20-colibri.dtsi"
9 compatible = "toradex,colibri_t20-eval-v3", "toradex,colibri_t20",
22 stdout-path = "serial0:115200n8";
27 rgb {
35 hdmi-supply = <&reg_5v0>;
41 bl-on {
49 hotplug-detect {
[all …]
Dstm32mp15xx-dhcor-avenger96.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
3 * Copyright (C) Linaro Ltd 2019 - All Rights Reserved
9 #include "stm32mp15xx-dhcor-io1v8.dtsi"
22 cec_clock: clk-cec-fixed {
23 #clock-cells = <0>;
24 compatible = "fixed-clock";
25 clock-frequency = <24000000>;
29 stdout-path = "serial0:115200n8";
32 hdmi-out {
33 compatible = "hdmi-connector";
[all …]
Dstm32429i-eval.dts2 * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
4 * This file is dual-licensed: you can use it either under the terms
22 * MA 02110-1301 USA
48 /dts-v1/;
50 #include "stm32f429-pinctrl.dtsi"
51 #include <dt-bindings/input/input.h>
52 #include <dt-bindings/gpio/gpio.h>
55 model = "STMicroelectronics STM32429i-EVAL board";
56 compatible = "st,stm32429i-eval", "st,stm32f429";
60 stdout-path = "serial0:115200n8";
[all …]
Dr8a7790-stout.dts1 // SPDX-License-Identifier: GPL-2.0
8 /dts-v1/;
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/input/input.h>
23 stdout-path = "serial0:115200n8";
32 compatible = "gpio-leds";
47 fixedregulator3v3: regulator-3v3 {
48 compatible = "regulator-fixed";
49 regulator-name = "fixed-3.3V";
50 regulator-min-microvolt = <3300000>;
[all …]
Dtegra20-acer-a500-picasso.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/atmel-maxtouch.h>
5 #include <dt-bindings/input/gpio-keys.h>
6 #include <dt-bindings/input/input.h>
7 #include <dt-bindings/thermal/thermal.h>
10 #include "tegra20-cpu-opp.dtsi"
11 #include "tegra20-cpu-opp-microvolt.dtsi"
32 * pre-existing /chosen node to be available to insert the
41 reserved-memory {
[all …]
Dtegra20-harmony.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/input.h>
18 stdout-path = "serial0:115200n8";
27 rgb {
37 hdmi-supply = <&vdd_5v0_hdmi>;
38 vdd-supply = <&hdmi_vdd_reg>;
39 pll-supply = <&hdmi_pll_reg>;
41 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
42 nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
[all …]
Dtegra30-apalis-v1.1.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
16 avdd-pexa-supply = <&vdd2_reg>;
17 avdd-pexb-supply = <&vdd2_reg>;
18 avdd-pex-pll-supply = <&vdd2_reg>;
19 avdd-plle-supply = <&ldo6_reg>;
20 hvdd-pex-supply = <&reg_module_3v3>;
21 vddio-pex-ctl-supply = <&reg_module_3v3>;
22 vdd-pexa-supply = <&vdd2_reg>;
23 vdd-pexb-supply = <&vdd2_reg>;
27 nvidia,num-lanes = <4>;
[all …]
Dtegra30-apalis.dtsi1 // SPDX-License-Identifier: GPL-2.0
15 avdd-pexa-supply = <&vdd2_reg>;
16 avdd-pexb-supply = <&vdd2_reg>;
17 avdd-pex-pll-supply = <&vdd2_reg>;
18 avdd-plle-supply = <&ldo6_reg>;
19 hvdd-pex-supply = <&reg_module_3v3>;
20 vddio-pex-ctl-supply = <&reg_module_3v3>;
21 vdd-pexa-supply = <&vdd2_reg>;
22 vdd-pexb-supply = <&vdd2_reg>;
26 nvidia,num-lanes = <4>;
[all …]
Dtegra30-cardhu.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/input/input.h>
3 #include <dt-bindings/thermal/thermal.h>
5 #include "tegra30-cpu-opp.dtsi"
6 #include "tegra30-cpu-opp-microvolt.dtsi"
16 * use tegra30-cardhu-a02.dts, Cardhu fab version A04 and later, use
17 * tegra30-cardhu-a04.dts.
20 * The sticker will have number like 600-81291-1000-002 C.3. In this 4th
22 * The (downstream internal) U-Boot of Cardhu display the board-id as
43 stdout-path = "serial0:115200n8";
[all …]
Dtegra20-ventana.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/input.h>
5 #include <dt-bindings/thermal/thermal.h>
7 #include "tegra20-cpu-opp.dtsi"
8 #include "tegra20-cpu-opp-microvolt.dtsi"
21 stdout-path = "serial0:115200n8";
30 rgb {
40 vdd-supply = <&hdmi_vdd_reg>;
41 pll-supply = <&hdmi_pll_reg>;
[all …]
Dtegra20-paz00.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/input.h>
5 #include <dt-bindings/thermal/thermal.h>
8 #include "tegra20-cpu-opp.dtsi"
9 #include "tegra20-cpu-opp-microvolt.dtsi"
23 stdout-path = "serial0:115200n8";
32 rgb {
42 vdd-supply = <&hdmi_vdd_reg>;
43 pll-supply = <&hdmi_pll_reg>;
[all …]
Dtegra30-asus-nexus7-grouper-common.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/input/gpio-keys.h>
4 #include <dt-bindings/input/input.h>
5 #include <dt-bindings/power/summit,smb347-charger.h>
6 #include <dt-bindings/thermal/thermal.h>
9 #include "tegra30-cpu-opp.dtsi"
10 #include "tegra30-cpu-opp-microvolt.dtsi"
26 * pre-existing /chosen node to be available to insert the
35 reserved-memory {
36 #address-cells = <1>;
[all …]
Dtegra20-seaboard.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/input.h>
18 stdout-path = "serial0:115200n8";
27 rgb {
37 vdd-supply = <&hdmi_vdd_reg>;
38 pll-supply = <&hdmi_pll_reg>;
39 hdmi-supply = <&vdd_hdmi>;
41 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
42 nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
[all …]
Dtegra30-colibri.dtsi1 // SPDX-License-Identifier: GPL-2.0
15 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
16 nvidia,hpd-gpio =
18 pll-supply = <&reg_1v8_avdd_hdmi_pll>;
19 vdd-supply = <&reg_3v3_avdd_hdmi>;
24 pinctrl-names = "default";
25 pinctrl-0 = <&state_default>;
28 /* Analogue Audio (On-module) */
29 clk1-out-pw4 {
34 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
[all …]
/Linux-v5.15/Documentation/devicetree/bindings/display/tegra/
Dnvidia,tegra20-host1x.txt4 - compatible: "nvidia,tegra<chip>-host1x"
5 - reg: Physical base address and length of the controller's registers.
6 For pre-Tegra186, one entry describing the whole register area.
7 For Tegra186, one entry for each entry in reg-names:
8 "vm" - VM region assigned to Linux
9 "hypervisor" - Hypervisor region (only if Linux acts as hypervisor)
10 - interrupts: The interrupt outputs from the controller.
11 - #address-cells: The number of cells used to represent physical base addresses
13 - #size-cells: The number of cells used to represent the size of an address
15 - ranges: The mapping of the host1x address space to the CPU address space.
[all …]
/Linux-v5.15/drivers/gpu/drm/panel/
Dpanel-novatek-nt35510.c1 // SPDX-License-Identifier: GPL-2.0-only
16 * per-panel, e.g. for physical size.
20 * The NT35510 can also use an RGB (DPI) interface combined with an
74 #define NT35510_DOPCTR_0_N565 BIT(2) /* RGB or BGR pixel format */
76 #define NT35510_DOPCTR_1_CRGB BIT(3) /* RGB or BGR byte order */
128 * struct nt35510_config - the display-specific NT35510 configuration
154 * +------------------------------------------->
180 * @bt1ctr: setting for boost power control for the AVDD step-up
183 * frequency for the step-up circuit:
193 * amplification for the the step-up circuit:
[all …]
/Linux-v5.15/drivers/gpu/drm/exynos/
Dexynos_hdmi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Seung-Woo Kim <sw0312.kim@samsung.com>
9 * Based on drivers/media/video/s5p-tv/hdmi_drv.c
33 #include <sound/hdmi-codec.h>
34 #include <media/cec-notifier.h>
44 #include "regs-hdmi.h"
74 static const char * const supply[] = { variable
75 "vdd",
105 * required parents of clock when HDMI-PHY is respectively off or on.
137 struct regulator_bulk_data regul_bulk[ARRAY_SIZE(supply)];
[all …]