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/Linux-v6.1/Documentation/devicetree/bindings/usb/
Dmsm-hsusb.txt6 - compatible: Should contain "qcom,ehci-host"
7 - regs: offset and length of the register set in the memory map
8 - usb-phy: phandle for the PHY device
13 compatible = "qcom,ehci-host";
15 usb-phy = <&usb_otg>;
18 USB PHY with optional OTG:
21 - compatible: Should contain:
22 "qcom,usb-otg-ci" for chipsets with ChipIdea 45nm PHY
23 "qcom,usb-otg-snps" for chipsets with Synopsys 28nm PHY
25 - regs: Offset and length of the register set in the memory map
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Ddwc2.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/usb/dwc2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: DesignWare HS OTG USB 2.0 controller Bindings
10 - Rob Herring <robh@kernel.org>
13 - $ref: usb-drd.yaml#
14 - $ref: usb-hcd.yaml#
19 - const: brcm,bcm2835-usb
20 - const: hisilicon,hi6220-usb
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Dmediatek,mtu3.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/usb/mediatek,mtu3.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Chunfeng Yun <chunfeng.yun@mediatek.com>
14 - $ref: "usb-drd.yaml"
23 - enum:
24 - mediatek,mt2712-mtu3
25 - mediatek,mt8173-mtu3
26 - mediatek,mt8183-mtu3
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Damlogic,meson-g12a-usb-ctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: "http://devicetree.org/schemas/usb/amlogic,meson-g12a-usb-ctrl.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
8 title: Amlogic Meson G12A DWC3 USB SoC Controller Glue
11 - Neil Armstrong <neil.armstrong@linaro.org>
14 The Amlogic G12A embeds a DWC3 USB IP Core configured for USB2 and USB3
15 in host-only mode, and a DWC2 IP Core configured for USB2 peripheral mode
20 One of the USB2 PHYs can be re-routed in peripheral mode to a DWC2 USB IP.
23 connected to the Glue to serve as OTG ID change detection.
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Domap-usb.txt4 - compatible : Should be "ti,omap4-musb" or "ti,omap3-musb"
5 - ti,hwmods : must be "usb_otg_hs"
6 - multipoint : Should be "1" indicating the musb controller supports
7 multipoint. This is a MUSB configuration-specific setting.
8 - num-eps : Specifies the number of endpoints. This is also a
9 MUSB configuration-specific setting. Should be set to "16"
10 - ram-bits : Specifies the ram address size. Should be set to "12"
11 - interface-type : This is a board specific setting to describe the type of
14 - mode : Should be "3" to represent OTG. "1" signifies HOST and "2"
16 - power : Should be "50". This signifies the controller can supply up to
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Dci-hdrc-usb2.txt1 * USB2 ChipIdea USB controller for ci13xxx
4 - compatible: should be one of:
5 "fsl,imx23-usb"
6 "fsl,imx27-usb"
7 "fsl,imx28-usb"
8 "fsl,imx6q-usb"
9 "fsl,imx6sl-usb"
10 "fsl,imx6sx-usb"
11 "fsl,imx6ul-usb"
12 "fsl,imx7d-usb"
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/Linux-v6.1/Documentation/devicetree/bindings/power/supply/
Dqcom,pm8941-charger.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/power/supply/qcom,pm8941-charger.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Switch-Mode Battery Charger and Boost
10 - Sebastian Reichel <sre@kernel.org>
15 - qcom,pm8226-charger
16 - qcom,pm8941-charger
23 - description: charge done
24 - description: charge fast mode
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Dmt6360_charger.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/power/supply/mt6360_charger.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Gene Chen <gene_chen@richtek.com>
14 Provides Battery Charger, Boost for OTG devices and BC1.2 detection.
18 const: mediatek,mt6360-chg
20 richtek,vinovp-microvolt:
21 description: Maximum CHGIN regulation voltage in uV.
25 usb-otg-vbus-regulator:
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Dmediatek,mt6370-charger.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/power/supply/mediatek,mt6370-charger.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - ChiaEn Wu <chiaen_wu@richtek.com>
14 Provides Battery Charger, Boost for OTG devices and BC1.2 detection.
18 const: mediatek,mt6370-charger
23 We need to use the IRQ "MT6370_IRQ_OVPCTRL_UVP_D" to know when USB
24 is plugged in, and then the driver will enable BC1.2 detection.
31 In summary, "MT6370_IRQ_OVPCTRL_UVP_D", "MT6370_IRQ_ATTACH" and
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Dsummit,smb347-charger.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/power/supply/summit,smb347-charger.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - David Heidelberg <david@ixit.cz>
11 - Dmitry Osipenko <digetx@gmail.com>
16 - summit,smb345
17 - summit,smb347
18 - summit,smb358
26 monitored-battery:
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Dbq24190.yaml1 # SPDX-License-Identifier: GPL-2.0
4 ---
5 $id: http://devicetree.org/schemas/power/supply/bq24190.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Binding for TI BQ2419x Li-Ion Battery Charger
11 - Sebastian Reichel <sre@kernel.org>
14 - $ref: power-supply.yaml#
19 - ti,bq24190
20 - ti,bq24192
21 - ti,bq24192i
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/Linux-v6.1/Documentation/devicetree/bindings/phy/
Dnvidia,tegra124-xusb-padctl.txt6 is controlled by a HW block referred to as a "pad" in the Tegra hardware
11 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
12 super-speed USB. Other lanes are for various types of low-speed, full-speed
13 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
14 contains a software-configurable mux that sits between the I/O controller
17 In addition to per-lane configuration, USB 3.0 ports may require additional
18 settings on a per-board basis.
20 Pads will be represented as children of the top-level XUSB pad controller
23 PHY bindings, as described by the phy-bindings.txt file in this directory.
27 "port" is typically used to denote the physical USB receptacle. The device
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Dphy-stm32-usbphyc.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/phy-stm32-usbphyc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STM32 USB HS PHY controller binding
13 selects either OTG or HOST controller for the second PHY port. It also sets
22 |_ PHY port#2 ----| |________________
24 |_ UTMI switch_______| OTG controller
27 - Amelie Delaunay <amelie.delaunay@foss.st.com>
31 const: st,stm32mp1-usbphyc
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Drenesas,usb2-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/renesas,usb2-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Car generation 3 USB 2.0 PHY
10 - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
15 - items:
16 - const: renesas,usb2-phy-r8a77470 # RZ/G1C
18 - items:
19 - enum:
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/Linux-v6.1/arch/mips/boot/dts/ingenic/
Dgcw0.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
5 #include <dt-bindings/clock/ingenic,tcu.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/iio/adc/ingenic,adc.h>
9 #include <dt-bindings/input/input.h>
29 stdout-path = "serial2:57600n8";
33 compatible = "regulator-fixed";
34 regulator-name = "vcc";
36 regulator-min-microvolt = <3300000>;
[all …]
/Linux-v6.1/arch/arm/boot/dts/
Drk3188-bqedison2qc.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
8 #include <dt-bindings/i2c/i2c.h>
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
14 model = "BQ Edison2 Quad-Core";
15 compatible = "mundoreader,bq-edison2qc", "rockchip,rk3188";
29 compatible = "pwm-backlight";
30 power-supply = <&vsys>;
34 gpio-keys {
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Drk3288-veyron-fievel.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 /dts-v1/;
9 #include "rk3288-veyron.dtsi"
10 #include "rk3288-veyron-analog-audio.dtsi"
14 compatible = "google,veyron-fievel-rev8", "google,veyron-fievel-rev7",
15 "google,veyron-fievel-rev6", "google,veyron-fievel-rev5",
16 "google,veyron-fievel-rev4", "google,veyron-fievel-rev3",
17 "google,veyron-fievel-rev2", "google,veyron-fievel-rev1",
18 "google,veyron-fievel-rev0", "google,veyron-fievel",
22 compatible = "regulator-fixed";
[all …]
Dstm32mp15xx-dhcom-picoitx.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
6 #include <dt-bindings/input/input.h>
7 #include <dt-bindings/pwm/pwm.h>
17 stdout-path = "serial0:115200n8";
21 compatible = "gpio-leds";
23 led-0 {
26 default-state = "off";
45 * NOTE: The USB Port on the PicoITX needs a PWR_EN signal to enable
46 * port power. This signal should be handled by USB power sequencing
47 * in order to turn on port power when USB bus is powered up, but so
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/Linux-v6.1/drivers/usb/phy/
Dphy-ab8500-usb.c1 // SPDX-License-Identifier: GPL-2.0+
3 * USB transceiver driver for AB8500 family chips
5 * Copyright (C) 2010-2013 ST-Ericsson AB
13 #include <linux/usb/otg.h>
22 #include <linux/usb/musb-ux500.h>
56 /* Usb line status register */
121 /* Driver is using the ab-iddet driver*/
152 abx500_set_register_interruptible(ab->dev, in ab8500_usb_wd_workaround()
159 abx500_set_register_interruptible(ab->dev, in ab8500_usb_wd_workaround()
167 abx500_set_register_interruptible(ab->dev, in ab8500_usb_wd_workaround()
[all …]
Dphy-generic.c1 // SPDX-License-Identifier: GPL-2.0+
3 * NOP USB transceiver for all USB transceiver which are either built-in
4 * into USB IP or which are mostly autonomous.
16 #include <linux/dma-mapping.h>
17 #include <linux/usb/gadget.h>
18 #include <linux/usb/otg.h>
19 #include <linux/usb/usb_phy_generic.h>
27 #include "phy-generic.h"
48 struct usb_phy_generic *nop = dev_get_drvdata(x->dev); in nop_set_suspend()
50 if (!IS_ERR(nop->clk)) { in nop_set_suspend()
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/Linux-v6.1/Documentation/devicetree/bindings/mfd/
Dx-powers,axp152.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mfd/x-powers,axp152.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: X-Powers AXP PMIC
10 - Chen-Yu Tsai <wens@csie.org>
13 - if:
18 - x-powers,axp152
19 - x-powers,axp202
20 - x-powers,axp209
[all …]
/Linux-v6.1/arch/arm64/boot/dts/rockchip/
Drk3308-rock-pi-s.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
21 stdout-path = "serial0:1500000n8";
25 compatible = "gpio-leds";
26 pinctrl-names = "default";
27 pinctrl-0 = <&green_led_gio>, <&heartbeat_led_gpio>;
29 green-led {
30 default-state = "on";
33 linux,default-trigger = "default-on";
36 blue-led {
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Drk3566-roc-pc.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 /dts-v1/;
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include <dt-bindings/soc/rockchip,vop2.h>
12 compatible = "firefly,rk3566-roc-pc", "rockchip,rk3566";
21 stdout-path = "serial2:1500000n8";
24 gmac1_clkin: external-gmac1-clock {
25 compatible = "fixed-clock";
26 clock-frequency = <125000000>;
[all …]
/Linux-v6.1/drivers/usb/dwc2/
Dcore.h1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
3 * core.h - DesignWare HS OTG Controller common declarations
5 * Copyright (C) 2004-2013 Synopsys, Inc.
14 #include <linux/usb/gadget.h>
15 #include <linux/usb/otg.h>
16 #include <linux/usb/phy.h>
21 * - no_printk: Disable tracing
22 * - pr_info: Print this info to the console
23 * - trace_printk: Print this info to trace buffer (good for verbose logging)
32 dev_name(hsotg->dev), ##__VA_ARGS__)
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Dplatform.c1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * platform.c - DesignWare HS OTG Controller platform driver
13 #include <linux/dma-mapping.h>
18 #include <linux/platform_data/s3c-hsotg.h>
21 #include <linux/usb/of.h>
34 * or otg. Check that all these values are compatible and adjust the
39 * ------------------------------
41 * HST DEV any : ---
42 * HST OTG any : HST
44 * DEV HST any : ---
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