Searched +full:uniphier +full:- +full:pro5 +full:- +full:pcie +full:- +full:ep (Results 1 – 4 of 4) sorted by relevance
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/pci/socionext,uniphier-pcie-ep.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: Socionext UniPhier PCIe endpoint controller10 UniPhier PCIe endpoint controller is based on the Synopsys DesignWare11 PCI core. It shares common features with the PCIe DesignWare core and13 Documentation/devicetree/bindings/pci/designware-pcie.txt.16 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>19 - $ref: "pci-ep.yaml#"[all …]
1 // SPDX-License-Identifier: GPL-2.0+ OR MIT3 // Device Tree Source for UniPhier Pro5 SoC5 // Copyright (C) 2015-2016 Socionext Inc.9 compatible = "socionext,uniphier-pro5";10 #address-cells = <1>;11 #size-cells = <1>;14 #address-cells = <1>;15 #size-cells = <0>;19 compatible = "arm,cortex-a9";22 enable-method = "psci";[all …]
1 # SPDX-License-Identifier: GPL-2.023 bool "TI DRA7xx PCIe controller Host Mode"31 Enables support for the PCIe controller in the DRA7xx SoC to work in32 host mode. There are two instances of PCIe controller in DRA7xx.33 This controller can work either as EP or RC. In order to enable34 host-specific features PCI_DRA7XX_HOST must be selected and in order35 to enable device-specific features PCI_DRA7XX_EP must be selected.39 bool "TI DRA7xx PCIe controller Endpoint Mode"46 Enables support for the PCIe controller in the DRA7xx SoC to work in47 endpoint mode. There are two instances of PCIe controller in DRA7xx.[all …]
1 // SPDX-License-Identifier: GPL-2.03 * PCIe endpoint controller driver for UniPhier SoCs19 #include "pcie-designware.h"66 #define to_uniphier_pcie(x) dev_get_drvdata((x)->dev)73 val = readl(priv->base + PCL_APP_READY_CTRL); in uniphier_pcie_ltssm_enable()78 writel(val, priv->base + PCL_APP_READY_CTRL); in uniphier_pcie_ltssm_enable()86 val = readl(priv->base + PCL_RSTCTRL2); in uniphier_pcie_phy_reset()91 writel(val, priv->base + PCL_RSTCTRL2); in uniphier_pcie_phy_reset()98 /* set EP mode */ in uniphier_pcie_init_ep()99 val = readl(priv->base + PCL_MODE); in uniphier_pcie_init_ep()[all …]
