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/Linux-v6.1/Documentation/devicetree/bindings/phy/
Dqcom,qmp-ufs-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,qmp-ufs-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm QMP PHY controller (UFS)
10 - Vinod Koul <vkoul@kernel.org>
14 controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
19 - qcom,msm8996-qmp-ufs-phy
20 - qcom,msm8998-qmp-ufs-phy
21 - qcom,sc8180x-qmp-ufs-phy
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Dmediatek,ufs-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/phy/mediatek,ufs-phy.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: MediaTek Universal Flash Storage (UFS) M-PHY binding
11 - Stanley Chu <stanley.chu@mediatek.com>
12 - Chunfeng Yun <chunfeng.yun@mediatek.com>
15 UFS M-PHY nodes are defined to describe on-chip UFS M-PHY hardware macro.
16 Each UFS M-PHY node should have its own node.
17 To bind UFS M-PHY with UFS host controller, the controller node should
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Dsamsung,ufs-phy.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/samsung,ufs-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung SoC series UFS PHY
10 - Alim Akhtar <alim.akhtar@samsung.com>
13 "#phy-cells":
18 - samsung,exynos7-ufs-phy
19 - samsung,exynosautov9-ufs-phy
20 - tesla,fsd-ufs-phy
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/Linux-v6.1/Documentation/devicetree/bindings/ufs/
Dhisilicon,ufs.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/ufs/hisilicon,ufs.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: HiSilicon Universal Flash Storage (UFS) Controller
10 - Li Wei <liwei213@huawei.com>
12 # Select only our matches, not all jedec,ufs
18 - hisilicon,hi3660-ufs
19 - hisilicon,hi3670-ufs
21 - compatible
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Dti,j721e-ufs.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/ufs/ti,j721e-ufs.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI J721e UFS Host Controller Glue Driver
10 - Vignesh Raghavendra <vigneshr@ti.com>
15 - const: ti,j721e-ufs
19 description: address of TI UFS glue registers
23 description: phandle to the M-PHY clock
25 power-domains:
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Dqcom,ufs.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/ufs/qcom,ufs.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Universal Flash Storage (UFS) Controller
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
11 - Andy Gross <agross@kernel.org>
13 # Select only our matches, not all jedec,ufs-2.0
20 - compatible
25 - enum:
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Dsamsung,exynos-ufs.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/ufs/samsung,exynos-ufs.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung SoC series UFS host controller
10 - Alim Akhtar <alim.akhtar@samsung.com>
13 Each Samsung UFS host controller instance should have its own node.
16 - $ref: ufs-common.yaml
21 - samsung,exynos7-ufs
22 - samsung,exynosautov9-ufs
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Dmediatek,ufs.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/ufs/mediatek,ufs.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Mediatek Universal Flash Storage (UFS) Controller
10 - Stanley Chu <stanley.chu@mediatek.com>
13 - $ref: ufs-common.yaml
18 - mediatek,mt8183-ufshci
19 - mediatek,mt8192-ufshci
24 clock-names:
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Drenesas,ufs.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ufs/renesas,ufs.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Car UFS Host Controller
10 - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
13 - $ref: ufs-common.yaml
17 const: renesas,r8a779f0-ufs
23 maxItems: 2
25 clock-names:
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Dcdns,ufshc.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/ufs/cdns,ufshc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cadence Universal Flash Storage (UFS) Controller
10 - Jan Kotas <jank@cadence.com>
12 # Select only our matches, not all jedec,ufs-2.0
18 - cdns,ufshc
19 - cdns,ufshc-m31-16nm
21 - compatible
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Dsnps,tc-dwc-g210.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/ufs/snps,tc-dwc-g210.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DesignWare Universal Flash Storage (UFS) Controller
10 - Li Wei <liwei213@huawei.com>
12 # Select only our matches, not all jedec,ufs
18 - snps,dwc-ufshcd-1.40a
20 - compatible
23 - $ref: ufs-common.yaml
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Dufs-common.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/ufs/ufs-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Common properties for Universal Flash Storage (UFS) Host Controllers
10 - Alim Akhtar <alim.akhtar@samsung.com>
11 - Avri Altman <avri.altman@wdc.com>
16 clock-names: true
18 freq-table-hz:
21 - description: Minimum frequency for given clock in Hz
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/Linux-v6.1/Documentation/scsi/
Dufs.rst1 .. SPDX-License-Identifier: GPL-2.0
11 2. UFS Architecture Overview
13 2.2 UFS Transport Protocol (UTP) layer
14 2.3 UFS Interconnect (UIC) Layer
16 3.1 UFS controller initialization
18 3.3 UFS error handling
21 5. UFS Reference Clock Frequency configuration
27 Universal Flash Storage (UFS) is a storage specification for flash devices.
29 embedded and removable flash memory-based storage in mobile
31 is defined by JEDEC Solid State Technology Association. UFS is based
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/Linux-v6.1/include/ufs/
Dufs_quirks.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2014-2016, The Linux Foundation. All rights reserved.
22 * ufs_dev_quirk - ufs device quirk info
23 * @card: ufs card details
33 * Some vendor's UFS device sends back to back NACs for the DL data frames
35 * such UFS devices send back to back NAC without waiting for new
42 * - As soon as SW sees the DL NAC error, it should schedule the error handler
43 * - Error handler would sleep for 50ms to see if there are any fatal errors
44 * raised by UFS controller.
45 * - If there are fatal errors then SW does normal error recovery.
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Dufshcd.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 * Copyright (C) 2011-2013 Samsung India Software Operations
5 * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
16 #include <linux/blk-crypto-profile.h>
17 #include <linux/blk-mq.h>
21 #include <ufs/unipro.h>
22 #include <ufs/ufs.h>
23 #include <ufs/ufs_quirks.h>
24 #include <ufs/ufshci.h>
61 * struct uic_command - UIC command structure
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Dufs.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 * Copyright (C) 2011-2013 Samsung India Software Operations
20 #define QUERY_DESC_MIN_SIZE 2
21 #define QUERY_DESC_HDR_SIZE 2
22 #define QUERY_OSF_SIZE (GENERAL_UPIU_REQUEST_SIZE - \
30 * UFS device may have standard LUs and LUN id could be from 0x00 to
32 * UFS device may also have the Well Known LUs (also referred as W-LU)
33 * which again could be from 0x00 to 0x7F. For W-LUs, device only use
34 * the "Extended Addressing Format" which means the W-LUNs would be
36 * This means max. LUN number reported from UFS device could be 0xC17F.
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/Linux-v6.1/drivers/ufs/host/
Dufs-exynos.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * UFS Host Controller driver for Exynos specific extensions
5 * Copyright (C) 2014-2015 Samsung Electronics Co., Ltd.
21 #include <ufs/ufshcd.h>
22 #include "ufshcd-pltfrm.h"
23 #include <ufs/ufshci.h>
24 #include <ufs/unipro.h>
26 #include "ufs-exynos.h"
56 #define REFCLK_STOP BIT(2)
82 /* FSYS UFS Shareability */
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Dufs-exynos.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * UFS Host Controller driver for Exynos specific extensions
5 * Copyright (C) 2014-2015 Samsung Electronics Co., Ltd.
102 #define UNIPRO_PCLK_PERIOD(ufs) (NSEC_PER_SEC / ufs->pclk_rate) argument
106 /* vendor specific pre-defined parameters */
108 #define FAST 2
167 int (*drv_init)(struct device *dev, struct exynos_ufs *ufs);
168 int (*pre_link)(struct exynos_ufs *ufs);
169 int (*post_link)(struct exynos_ufs *ufs);
170 int (*pre_pwr_change)(struct exynos_ufs *ufs,
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Dufs-qcom.h1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
8 #include <linux/reset-controller.h>
10 #include <ufs/ufshcd.h>
27 /* vendor specific pre-defined parameters */
29 #define FAST 2
33 /* QCOM UFS host controller vendor specific registers */
52 * QCOM UFS host controller vendor specific registers
58 /* QCOM UFS host controller vendor specific debug registers */
88 #define TXUC_HW_CGC_EN (1 << 2)
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Dcdns-pltfrm.c1 // SPDX-License-Identifier: GPL-2.0
3 * Platform UFS Host driver for Cadence controller
19 #include "ufshcd-pltfrm.h"
27 * cdns_ufs_dme_attr_val - for storing L4 attributes
33 * cdns_ufs_get_l4_attr - get L4 attributes on local side
42 &host->cdns_ufs_dme_attr_val[0]); in cdns_ufs_get_l4_attr()
44 &host->cdns_ufs_dme_attr_val[1]); in cdns_ufs_get_l4_attr()
46 &host->cdns_ufs_dme_attr_val[2]); in cdns_ufs_get_l4_attr()
48 &host->cdns_ufs_dme_attr_val[3]); in cdns_ufs_get_l4_attr()
50 &host->cdns_ufs_dme_attr_val[4]); in cdns_ufs_get_l4_attr()
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/Linux-v6.1/Documentation/ABI/testing/
Dsysfs-driver-ufs3 Contact: linux-scsi@vger.kernel.org
5 This file contains the auto-hibernate idle timer setting of a
6 UFS host controller. A value of '0' means auto-hibernate is not
8 idle time before the UFS host controller will autonomously put
11 10-bit values with a power-of-ten multiplier which allows a
12 maximum value of 102300000. Refer to the UFS Host Controller
16 What: /sys/bus/platform/devices/*.ufs/device_descriptor/device_type
19 Description: This file shows the device type. This is one of the UFS
21 the descriptor could be found at UFS specifications 2.1.
26 What: /sys/bus/platform/devices/*.ufs/device_descriptor/device_class
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/Linux-v6.1/Documentation/devicetree/bindings/clock/
Dqcom,gcc-sm8350.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,gcc-sm8350.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Vinod Koul <vkoul@kernel.org>
17 - dt-bindings/clock/qcom,gcc-sm8350.h
21 const: qcom,gcc-sm8350
25 - description: Board XO source
26 - description: Sleep clock source
27 - description: PLL test clock source (Optional clock)
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Dqcom,gcc-sc8280xp.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,gcc-sc8280xp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
17 - include/dt-bindings/clock/qcom,gcc-sc8280xp.h
21 const: qcom,gcc-sc8280xp
25 - description: XO reference clock
26 - description: Sleep clock
27 - description: UFS memory first RX symbol clock
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Dqcom,gcc-sm8450.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,gcc-sm8450.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Vinod Koul <vkoul@kernel.org>
17 - dt-bindings/clock/qcom,gcc-sm8450.h
21 const: qcom,gcc-sm8450
25 - description: Board XO source
26 - description: Sleep clock source
27 - description: PCIE 0 Pipe clock source (Optional clock)
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Dqcom,gcc-msm8996.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,gcc-msm8996.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Stephen Boyd <sboyd@kernel.org>
11 - Taniya Das <tdas@codeaurora.org>
18 - dt-bindings/clock/qcom,gcc-msm8996.h
22 const: qcom,gcc-msm8996
27 - description: XO source
28 - description: Second XO source
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