Home
last modified time | relevance | path

Searched +full:uart0 +full:- +full:pins (Results 1 – 25 of 449) sorted by relevance

12345678910>>...18

/Linux-v6.1/Documentation/devicetree/bindings/pinctrl/
Dimg,pistachio-pinctrl.txt6 controller on Pistachio has 99 pins, 90 of which are MFIOs which can be
8 each. The GPIO banks are represented as sub-nodes of the pad controller node.
10 Please refer to pinctrl-bindings.txt, ../gpio/gpio.txt, and
11 ../interrupt-controller/interrupts.txt for generic information regarding
15 --------------------------------------------
16 - compatible: "img,pistachio-system-pinctrl".
17 - reg: Address range of the pinctrl registers.
19 Required properties for GPIO bank sub-nodes:
20 --------------------------------------------
21 - interrupts: Interrupt line for the GPIO bank.
[all …]
Dnxp,lpc1850-scu.txt2 --------------------------------------------------------
5 - compatible : Should be "nxp,lpc1850-scu"
6 - reg : Address and length of the register set for the device
7 - clocks : Clock specifier (see clock bindings for details)
9 The lpc1850-scu driver uses the generic pin multiplexing and generic pin
10 configuration documented in pinctrl-bindings.txt.
13 - function
14 - pins
15 - bias-disable
16 - bias-pull-up
[all …]
Dmarvell,kirkwood-pinctrl.txt3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
7 - compatible: "marvell,88f6180-pinctrl",
8 "marvell,88f6190-pinctrl", "marvell,88f6192-pinctrl",
9 "marvell,88f6281-pinctrl", "marvell,88f6282-pinctrl",
10 "marvell,98dx4122-pinctrl", "marvell,98dx1135-pinctrl"
11 - reg: register specifier of MPP registers
14 It also support the 88f6281-based variant in the 98dx412x Bobcat SoCs.
16 Available mpp pins/groups and functions:
22 name pins functions
28 mpp4 4 gpio, nand(io6), uart0(rxd), ptp(clk)
[all …]
Dbitmain,bm1880-pinctrl.txt7 - compatible: Should be "bitmain,bm1880-pinctrl"
8 - reg: Offset and length of pinctrl space in SCTRL.
10 Please refer to pinctrl-bindings.txt in this directory for details of the
16 pin, a group, or a list of pins or groups. This configuration for BM1880 SoC
17 includes pinmux and various pin configuration parameters, such as pull-up,
24 The following generic properties as defined in pinctrl-bindings.txt are valid
29 - pins: An array of strings, each string containing the name of a pin.
30 Valid values for pins are:
32 MIO0 - MIO111
34 - groups: An array of strings, each string containing the name of a pin
[all …]
Dcnxt,cx92755-pinctrl.txt11 - compatible: Must be "cnxt,cx92755-pinctrl"
12 - reg: Base address of the General Purpose Pin Mapping register block and the
14 - gpio-controller: Marks the device node as a GPIO controller.
15 - #gpio-cells: Must be <2>. The first cell is the pin number and the
16 second cell is used to specify flags. See include/dt-bindings/gpio/gpio.h
22 compatible = "cnxt,cx92755-pinctrl";
24 gpio-controller;
25 #gpio-cells = <2>;
36 Each pin configuration node is a sub-node of the pin controller node and is a
40 Please refer to the pinctrl-bindings.txt in this directory for details of the
[all …]
Dmarvell,armada-370-pinctrl.txt3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
7 - compatible: "marvell,88f6710-pinctrl"
8 - reg: register specifier of MPP registers
10 Available mpp pins/groups and functions:
14 name pins functions
16 mpp0 0 gpio, uart0(rxd)
17 mpp1 1 gpo, uart0(txd)
18 mpp2 2 gpio, i2c0(sck), uart0(txd)
19 mpp3 3 gpio, i2c0(sda), uart0(rxd)
20 mpp4 4 gpio, vdd(cpu-pd)
[all …]
/Linux-v6.1/arch/arm/boot/dts/
Dlpc4350-hitex-eval.dts9 * Released under the terms of 3-clause BSD License
13 /dts-v1/;
18 #include "dt-bindings/input/input.h"
19 #include "dt-bindings/gpio/gpio.h"
23 compatible = "hitex,lpc4350-eval-board", "nxp,lpc4350";
26 serial0 = &uart0;
33 stdout-path = &uart0;
42 compatible = "gpio-keys-polled";
43 poll-interval = <100>;
97 compatible = "gpio-leds";
[all …]
Dlpc4357-ea4357-devkit.dts9 * Released under the terms of 3-clause BSD License
13 /dts-v1/;
18 #include "dt-bindings/input/input.h"
19 #include "dt-bindings/gpio/gpio.h"
23 compatible = "ea,lpc4357-developers-kit", "nxp,lpc4357", "nxp,lpc4350";
26 serial0 = &uart0;
33 stdout-path = &uart0;
42 compatible = "regulator-fixed";
43 regulator-name = "3v3-supply";
44 regulator-min-microvolt = <3300000>;
[all …]
Dkirkwood-openblocks_a6.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
5 #include "kirkwood-6282.dtsi"
9 compatible = "plathome,openblocks-a6", "marvell,kirkwood-88f6283", "marvell,kirkwood";
18 stdout-path = &uart0;
31 nr-ports = <1>;
44 pinctrl: pin-controller@10000 {
45 pinctrl-0 = <&pmx_dip_switches>;
46 pinctrl-names = "default";
48 pmx_uart0: pmx-uart0 {
[all …]
Dkirkwood-openblocks_a7.dts1 // SPDX-License-Identifier: GPL-2.0
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
11 /dts-v1/;
14 #include "kirkwood-6282.dtsi"
18 compatible = "plathome,openblocks-a7", "marvell,kirkwood-88f6283", "marvell,kirkwood";
27 stdout-path = &uart0;
40 nr-ports = <1>;
53 pinctrl: pin-controller@10000 {
54 pinctrl-0 = <&pmx_dip_switches &pmx_gpio_header
56 pinctrl-names = "default";
[all …]
Dmt7629-rfb.dts1 // SPDX-License-Identifier: GPL-2.0
7 /dts-v1/;
8 #include <dt-bindings/input/input.h>
13 compatible = "mediatek,mt7629-rfb", "mediatek,mt7629";
16 serial0 = &uart0;
20 stdout-path = "serial0:115200n8";
23 gpio-keys {
24 compatible = "gpio-keys";
26 button-reset {
32 button-wps {
[all …]
Dste-nomadik-s8815.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree for the ST-Ericsson Nomadik S8815 board
7 /dts-v1/;
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include "ste-nomadik-stn8815.dtsi"
12 model = "Calao Systems USB-S8815";
13 compatible = "calaosystems,usb-s8815";
20 serial0 = &uart0;
26 mmcsd-gpio {
27 gpio-hog;
[all …]
Dlpc4357-myd-lpc4357.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * MYIR Tech MYD-LPC4357 Development Board with 800x480 7" TFT panel
5 * Copyright (C) 2016-2018 Vladimir Zapolskiy <vz@mleia.com>
8 /dts-v1/;
13 #include <dt-bindings/gpio/gpio.h>
17 compatible = "myir,myd-lpc4357", "nxp,lpc4357";
20 stdout-path = "serial3:115200n8";
29 compatible = "gpio-leds";
30 pinctrl-names = "default";
31 pinctrl-0 = <&led_pins>;
[all …]
Dsama5d3_uart.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * sama5d3_uart.dtsi - Device Tree Include file for SAMA5D3 SoC with
9 #include <dt-bindings/pinctrl/at91.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/clock/at91.h>
12 #include <dt-bindings/mfd/at91-usart.h>
16 serial5 = &uart0;
23 uart0 {
24 pinctrl_uart0: uart0-0 {
25 atmel,pins =
[all …]
Dat91-smartkiz.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2017-2018 Overkiz SAS
8 /dts-v1/;
9 #include "at91-kizboxmini-common.dtsi"
23 serial5 = &uart0;
46 pinctrl_i2c1: i2c1-0 {
47 atmel,pins =
54 pinctrl_adc0_ad0: adc0_ad0-0 {
55 /* pull-up disable */
56 atmel,pins = <AT91_PIOB 11 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
[all …]
Ds3c2416-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include "s3c2410-pinctrl.h"
15 gpa: gpa-gpio-bank {
16 gpio-controller;
17 #gpio-cells = <2>;
20 gpb: gpb-gpio-bank {
21 gpio-controller;
22 #gpio-cells = <2>;
25 gpc: gpc-gpio-bank {
26 gpio-controller;
[all …]
Dspear310-evb.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
8 /dts-v1/;
13 compatible = "st,spear310-evb", "st,spear310";
14 #address-cells = <1>;
15 #size-cells = <1>;
23 pinctrl-names = "default";
24 pinctrl-0 = <&state_default>;
28 st,pins = "gpio0_pin0_grp",
37 st,pins = "i2c0_grp";
41 st,pins = "mii0_grp";
[all …]
Dspear320-evb.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
8 /dts-v1/;
13 compatible = "st,spear320-evb", "st,spear320";
14 #address-cells = <1>;
15 #size-cells = <1>;
23 st,pinmux-mode = <4>;
24 pinctrl-names = "default";
25 pinctrl-0 = <&state_default>;
29 st,pins = "i2c0_grp";
33 st,pins = "mii0_grp";
[all …]
/Linux-v6.1/arch/arm64/boot/dts/mediatek/
Dmt8195-evb.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 /dts-v1/;
11 compatible = "mediatek,mt8195-evb", "mediatek,mt8195";
14 serial0 = &uart0;
18 stdout-path = "serial0:921600n8";
32 pinctrl-names = "default";
33 pinctrl-0 = <&i2c0_pin>;
34 clock-frequency = <100000>;
39 pinctrl-names = "default";
40 pinctrl-0 = <&i2c1_pin>;
[all …]
/Linux-v6.1/arch/arm64/boot/dts/toshiba/
Dtmpv7708_pins.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 spi0_pins: spi0-pins {
8 spi1_pins: spi1-pins {
12 spi2_pins: spi2-pins {
16 spi3_pins: spi3-pins {
20 spi4_pins: spi4-pins {
24 spi5_pins: spi5-pins {
28 spi6_pins: spi6-pins {
32 uart0_pins: uart0-pins {
33 function = "uart0";
[all …]
/Linux-v6.1/arch/arm64/boot/dts/ti/
Dk3-am65-iot2050-common.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) Siemens AG, 2018-2021
12 #include "k3-am654.dtsi"
13 #include <dt-bindings/phy/phy.h>
23 stdout-path = "serial3:115200n8";
27 reserved-memory {
28 #address-cells = <2>;
29 #size-cells = <2>;
32 secure_ddr: secure-ddr@9e800000 {
33 reg = <0 0x9e800000 0 0x01800000>; /* for OP-TEE */
[all …]
/Linux-v6.1/arch/mips/boot/dts/mscc/
Dserval_common.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
10 serial0 = &uart0;
20 stdout-path = "serial0:115200n8";
23 i2c0_imux: i2c0-imux{
24 compatible = "i2c-mux-pinctrl";
25 #address-cells = <1>;
26 #size-cells = <0>;
27 i2c-parent = <&i2c0>;
28 pinctrl-names =
31 pinctrl-0 = <&i2cmux_0>;
[all …]
Dserval.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #address-cells = <1>;
8 #size-cells = <1>;
12 #address-cells = <1>;
13 #size-cells = <0>;
24 serial0 = &uart0;
28 cpuintc: interrupt-controller {
29 #address-cells = <0>;
30 #interrupt-cells = <1>;
31 interrupt-controller;
[all …]
/Linux-v6.1/arch/mips/boot/dts/img/
Dpistachio.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <dt-bindings/clock/pistachio-clk.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/mips-gic.h>
11 #include <dt-bindings/reset/pistachio-resets.h>
16 #address-cells = <1>;
17 #size-cells = <1>;
19 interrupt-parent = <&gic>;
22 #address-cells = <1>;
[all …]
/Linux-v6.1/arch/arm64/boot/dts/xilinx/
Dzynqmp-zc1751-xm016-dc2.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP zc1751-xm016-dc2
5 * (C) Copyright 2015 - 2021, Xilinx, Inc.
10 /dts-v1/;
13 #include "zynqmp-clk-ccf.dtsi"
14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
18 model = "ZynqMP zc1751-xm016-dc2 RevA";
19 compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
25 serial0 = &uart0;
[all …]

12345678910>>...18