| /Linux-v6.1/sound/drivers/ |
| D | serial-u16550.c | 157 static inline void snd_uart16550_add_timer(struct snd_uart16550 *uart) in snd_uart16550_add_timer() argument
159 if (!uart->timer_running) { in snd_uart16550_add_timer()
161 mod_timer(&uart->buffer_timer, jiffies + (HZ + 255) / 256); in snd_uart16550_add_timer()
162 uart->timer_running = 1; in snd_uart16550_add_timer()
166 static inline void snd_uart16550_del_timer(struct snd_uart16550 *uart) in snd_uart16550_del_timer() argument
168 if (uart->timer_running) { in snd_uart16550_del_timer()
169 del_timer(&uart->buffer_timer); in snd_uart16550_del_timer()
170 uart->timer_running = 0; in snd_uart16550_del_timer()
175 static inline void snd_uart16550_buffer_output(struct snd_uart16550 *uart) in snd_uart16550_buffer_output() argument
177 unsigned short buff_out = uart->buff_out; in snd_uart16550_buffer_output()
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| /Linux-v6.1/Documentation/devicetree/bindings/serial/ |
| D | mediatek,uart.yaml | 4 $id: http://devicetree.org/schemas/serial/mediatek,uart.yaml#
7 title: MediaTek Universal Asynchronous Receiver/Transmitter (UART)
16 The MediaTek UART is based on the basic 8250 UART and compatible
23 - const: mediatek,mt6577-uart
26 - mediatek,mt2701-uart
27 - mediatek,mt2712-uart
28 - mediatek,mt6580-uart
29 - mediatek,mt6582-uart
30 - mediatek,mt6589-uart
31 - mediatek,mt6755-uart
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| D | mvebu-uart.txt | 1 * Marvell UART : Non standard UART used in some of Marvell EBU SoCs
6 - "marvell,armada-3700-uart" for the standard variant of the UART
9 - "marvell,armada-3700-uart-ext" for the extended variant of the
10 UART (128 bytes FIFO, DMA, front interrupts, 8-bit or 32-bit
13 - clocks: UART reference clock used to derive the baudrate. If no clock
14 is provided (possible only with the "marvell,armada-3700-uart"
18 for standard variant of UART and UART2-clk for extended variant
19 of UART. TBG clock (with UART TBG divisors d1=d2=1) or xtal clock
23 (marvell,armada-3700-uart): "uart-sum", "uart-tx" and "uart-rx",
24 respectively the UART sum interrupt, the UART TX interrupt and
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| D | fsl-imx-uart.yaml | 4 $id: http://devicetree.org/schemas/serial/fsl-imx-uart.yaml#
7 title: Freescale i.MX Universal Asynchronous Receiver/Transmitter (UART)
19 - const: fsl,imx1-uart
20 - const: fsl,imx21-uart
23 - fsl,imx25-uart
24 - fsl,imx27-uart
25 - fsl,imx31-uart
26 - fsl,imx35-uart
27 - fsl,imx50-uart
28 - fsl,imx51-uart
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| D | snps-dw-apb-uart.yaml | 4 $id: http://devicetree.org/schemas/serial/snps-dw-apb-uart.yaml#
7 title: Synopsys DesignWare ABP UART
20 - renesas,r9a06g032-uart
21 - renesas,r9a06g033-uart
22 - const: renesas,rzn1-uart
25 - rockchip,px30-uart
26 - rockchip,rk1808-uart
27 - rockchip,rk3036-uart
28 - rockchip,rk3066-uart
29 - rockchip,rk3128-uart
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| D | samsung_uart.yaml | 7 title: Samsung S3C, S5P, Exynos, and S5L (Apple SoC) SoC UART Controller
14 Each Samsung UART should have an alias correctly numbered in the "aliases"
22 - const: samsung,exynosautov9-uart
23 - const: samsung,exynos850-uart
25 - apple,s5l-uart
26 - axis,artpec8-uart
27 - samsung,s3c2410-uart
28 - samsung,s3c2412-uart
29 - samsung,s3c2440-uart
30 - samsung,s3c6400-uart
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| D | 8250.yaml | 7 title: UART (Universal Asynchronous Receiver/Transmitter) bindings
29 const: mrvl,mmp-uart
61 - const: intel,xscale-uart
62 - const: mrvl,pxa-uart
63 - const: nuvoton,wpcm450-uart
64 - const: nuvoton,npcm750-uart
65 - const: nuvoton,npcm845-uart
66 - const: nvidia,tegra20-uart
67 - const: nxp,lpc3220-uart
82 - nxp,lpc1850-uart
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| D | amlogic,meson-uart.yaml | 5 $id: "http://devicetree.org/schemas/serial/amlogic,meson-uart.yaml#"
8 title: Amlogic Meson SoC UART Serial Interface
14 The Amlogic Meson SoC UART Serial Interface is present on a large range
25 - description: Always-on power domain UART controller
28 - amlogic,meson6-uart
29 - amlogic,meson8-uart
30 - amlogic,meson8b-uart
31 - amlogic,meson-gx-uart
32 - amlogic,meson-s4-uart
33 - const: amlogic,meson-ao-uart
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| D | sprd-uart.yaml | 5 $id: "http://devicetree.org/schemas/serial/sprd-uart.yaml#"
8 title: Spreadtrum serial UART
20 - sprd,sc9860-uart
21 - sprd,sc9863a-uart
22 - sprd,ums512-uart
23 - const: sprd,sc9836-uart
24 - const: sprd,sc9836-uart
38 "enable" for UART module enable clock, "uart" for UART clock, "source"
39 for UART source (parent) clock.
42 - const: uart
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| D | brcm,bcm7271-uart.yaml | 4 $id: http://devicetree.org/schemas/serial/brcm,bcm7271-uart.yaml#
16 The Broadcom UART is based on the basic 8250 UART but with
24 - brcm,bcm7271-uart
25 - brcm,bcm7278-uart
32 description: The UART register block and optionally the DMA register blocks.
35 - const: uart
37 - const: uart
54 description: The UART interrupt and optionally the DMA interrupt.
57 - const: uart
74 compatible = "brcm,bcm7271-uart";
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| D | 8250_omap.yaml | 20 - ti,am3352-uart
21 - ti,am4372-uart
22 - ti,am654-uart
23 - ti,dra742-uart
24 - ti,omap2-uart
25 - ti,omap3-uart
26 - ti,omap4-uart
29 - ti,am64-uart
30 - ti,j721e-uart
31 - const: ti,am654-uart
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| /Linux-v6.1/drivers/tty/serial/ |
| D | men_z135_uart.c | 3 * MEN 16z135 High Speed UART
132 * @uart: The UART port
136 static inline void men_z135_reg_set(struct men_z135_port *uart, in men_z135_reg_set() argument
139 struct uart_port *port = &uart->port; in men_z135_reg_set()
143 spin_lock_irqsave(&uart->lock, flags); in men_z135_reg_set()
149 spin_unlock_irqrestore(&uart->lock, flags); in men_z135_reg_set()
154 * @uart: The UART port
158 static void men_z135_reg_clr(struct men_z135_port *uart, in men_z135_reg_clr() argument
161 struct uart_port *port = &uart->port; in men_z135_reg_clr()
165 spin_lock_irqsave(&uart->lock, flags); in men_z135_reg_clr()
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| D | timbuart.c | 3 * timbuart.c timberdale FPGA UART driver
8 * Timberdale FPGA UART
55 struct timbuart_port *uart = in timbuart_start_tx() local
59 tasklet_schedule(&uart->tasklet); in timbuart_start_tx()
119 struct timbuart_port *uart = in timbuart_handle_tx_port() local
138 *ier |= uart->last_ier & TXFLAGS; in timbuart_handle_tx_port()
175 struct timbuart_port *uart = from_tasklet(uart, t, tasklet); in timbuart_tasklet() local
178 spin_lock(&uart->port.lock); in timbuart_tasklet()
180 isr = ioread32(uart->port.membase + TIMBUART_ISR); in timbuart_tasklet()
181 dev_dbg(uart->port.dev, "%s ISR: %x\n", __func__, isr); in timbuart_tasklet()
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| D | arc_uart.c | 3 * ARC On-Chip(fpga) UART Driver
17 * -New Serial Core based ARC UART driver
37 * ARC UART Hardware Specs
42 * UART Register set (this is not a Standards Compliant IP)
54 /* Bits for UART Status Reg (R/W) */
67 /* Uart bit fiddling helpers: lowest level */
75 /* Uart bit fiddling helpers: API level */
76 #define UART_SET_DATA(uart, val) UART_REG_SET(uart, R_DATA, val) argument
77 #define UART_GET_DATA(uart) UART_REG_GET(uart, R_DATA) argument
79 #define UART_SET_BAUDH(uart, val) UART_REG_SET(uart, R_BAUDH, val) argument
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| /Linux-v6.1/drivers/tty/serial/8250/ |
| D | 8250_tegra.c | 45 struct tegra_uart *uart; in tegra_uart_probe() local
50 uart = devm_kzalloc(&pdev->dev, sizeof(*uart), GFP_KERNEL); in tegra_uart_probe()
51 if (!uart) in tegra_uart_probe()
90 uart->rst = devm_reset_control_get_optional_shared(&pdev->dev, NULL); in tegra_uart_probe()
91 if (IS_ERR(uart->rst)) in tegra_uart_probe()
92 return PTR_ERR(uart->rst); in tegra_uart_probe()
96 uart->clk = devm_clk_get(&pdev->dev, NULL); in tegra_uart_probe()
97 if (IS_ERR(uart->clk)) { in tegra_uart_probe()
102 ret = clk_prepare_enable(uart->clk); in tegra_uart_probe()
106 port->uartclk = clk_get_rate(uart->clk); in tegra_uart_probe()
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| D | 8250_core.c | 276 * IIR bits on their UART, but it's specifically designed for in serial8250_backup_timeout()
277 * the "Diva" UART used on the management processor on many HP in serial8250_backup_timeout()
592 * Check whether an invalid uart number has been specified, and in univ8250_console_setup()
624 * console=uart[8250],io|mmio|mmio16|mmio32,<addr>[,<options>]
625 * console=uart[8250],0x<addr>[,<options>]
637 char match[] = "uart"; /* 8250-specific earlycon name */ in univ8250_console_match()
806 struct uart_8250_port uart; in serial8250_probe() local
809 memset(&uart, 0, sizeof(uart)); in serial8250_probe()
815 uart.port.iobase = p->iobase; in serial8250_probe()
816 uart.port.membase = p->membase; in serial8250_probe()
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| D | 8250_lpc18xx.c | 3 * Serial port driver for NXP LPC18xx/43xx UART
93 struct uart_8250_port uart; in lpc18xx_serial_probe() local
107 memset(&uart, 0, sizeof(uart)); in lpc18xx_serial_probe()
109 uart.port.membase = devm_ioremap(&pdev->dev, res->start, in lpc18xx_serial_probe()
111 if (!uart.port.membase) in lpc18xx_serial_probe()
120 dev_err(&pdev->dev, "uart clock not found\n"); in lpc18xx_serial_probe()
138 dev_err(&pdev->dev, "unable to enable uart clock\n"); in lpc18xx_serial_probe()
144 uart.port.line = ret; in lpc18xx_serial_probe()
149 spin_lock_init(&uart.port.lock); in lpc18xx_serial_probe()
150 uart.port.dev = &pdev->dev; in lpc18xx_serial_probe()
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| D | 8250_ingenic.c | 6 * Ingenic SoC UART support
132 OF_EARLYCON_DECLARE(jz4740_uart, "ingenic,jz4740-uart",
135 OF_EARLYCON_DECLARE(jz4770_uart, "ingenic,jz4770-uart",
138 OF_EARLYCON_DECLARE(jz4775_uart, "ingenic,jz4775-uart",
141 OF_EARLYCON_DECLARE(jz4780_uart, "ingenic,jz4780-uart",
144 OF_EARLYCON_DECLARE(x1000_uart, "ingenic,x1000-uart",
153 /* UART module enable */ in ingenic_uart_serial_out()
209 struct uart_8250_port uart = {}; in ingenic_uart_probe() local
235 spin_lock_init(&uart.port.lock); in ingenic_uart_probe()
236 uart.port.type = PORT_16550A; in ingenic_uart_probe()
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| D | 8250_pxa.c | 56 { .compatible = "mrvl,pxa-uart", },
57 { .compatible = "mrvl,mmp-uart", },
62 /* Uart divisor latch write */
92 struct uart_8250_port uart = {}; in serial_pxa_probe() local
119 uart.port.line = ret; in serial_pxa_probe()
121 uart.port.type = PORT_XSCALE; in serial_pxa_probe()
122 uart.port.iotype = UPIO_MEM32; in serial_pxa_probe()
123 uart.port.mapbase = mmres->start; in serial_pxa_probe()
124 uart.port.regshift = 2; in serial_pxa_probe()
125 uart.port.irq = irq; in serial_pxa_probe()
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| D | 8250_hp300.c | 63 /* Offset to UART registers from base of DCA */
160 struct uart_8250_port uart; in hpdca_init_one() local
169 memset(&uart, 0, sizeof(uart)); in hpdca_init_one()
172 uart.port.iotype = UPIO_MEM; in hpdca_init_one()
173 uart.port.flags = UPF_SKIP_TEST | UPF_SHARE_IRQ | UPF_BOOT_AUTOCONF; in hpdca_init_one()
174 uart.port.irq = d->ipl; in hpdca_init_one()
175 uart.port.uartclk = HPDCA_BAUD_BASE * 16; in hpdca_init_one()
176 uart.port.mapbase = (d->resource.start + UART_OFFSET); in hpdca_init_one()
177 uart.port.membase = (char *)(uart.port.mapbase + DIO_VIRADDRBASE); in hpdca_init_one()
178 uart.port.regshift = 1; in hpdca_init_one()
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| /Linux-v6.1/arch/mips/kernel/ |
| D | cps-vec-ns16550.S | 32 * _mips_cps_putc() - write a character to the UART
34 * @t9: UART base address
45 * _mips_cps_puts() - write a string to the UART
47 * @t9: UART base address
49 * Write a null-terminated ASCII string to the UART.
65 * _mips_cps_putx4 - write a 4b hex value to the UART
66 * @a0: the 4b value to write to the UART
67 * @t9: UART base address
69 * Write a single hexadecimal character to the UART.
82 * _mips_cps_putx8 - write an 8b hex value to the UART
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| /Linux-v6.1/include/uapi/linux/ |
| D | serial_core.h | 31 #define PORT_RM9000 16 /* PMC-Sierra RM9xxx internal UART */
32 #define PORT_OCTEON 17 /* Cavium OCTEON internal UART */
33 #define PORT_AR7 18 /* Texas Instruments AR7 internal UART */
34 #define PORT_U6_16550A 19 /* ST-Ericsson U6xxx internal UART */
35 #define PORT_TEGRA 20 /* NVIDIA Tegra internal UART */
36 #define PORT_XR17D15X 21 /* Exar XR17D15x UART */
37 #define PORT_LPC3220 22 /* NXP LPC32xx SoC "Standard" UART */
41 #define PORT_ALTR_16550_F32 26 /* Altera 16550 UART with 32 FIFOs */
42 #define PORT_ALTR_16550_F64 27 /* Altera 16550 UART with 64 FIFOs */
43 #define PORT_ALTR_16550_F128 28 /* Altera 16550 UART with 128 FIFOs */
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| /Linux-v6.1/arch/arm/include/debug/ |
| D | tegra.S | 45 #define checkuart(rp, rv, lhu, bit, uart) \ argument
50 /* Test UART's reset bit */ \
52 /* If set, can't use UART; jump to save no UART */ \
58 /* Test UART's clock enable bit */ \
60 /* If clear, can't use UART; jump to save no UART */ \
62 /* Passed all tests, load address of UART registers */ \
63 ldr rp, =TEGRA_UART##uart##_BASE ; \
64 /* Jump to save UART address */ \
85 cmp \rv, #2 @ 2 and 3 mean DCC, UART
89 11: lsr \rv, \rp, #15 @ 17:15 are UART ID
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| /Linux-v6.1/arch/arm/ |
| D | Kconfig.debug | 123 UART definition, as specified below. Attempting to boot the kernel
140 bool "Kernel low-level debugging via asm9260 UART"
144 their output to an UART or USART port on asm9260 based
234 bool "Kernel low-level debugging on BCM2835 PL011 UART"
239 bool "Kernel low-level debugging on BCM2836 PL011 UART"
262 bool "Kernel low-level debugging messages via BCM KONA UART"
273 bool "Kernel low-level debugging on BCM63XX UART"
277 bool "Marvell Berlin SoC Debug UART"
285 bool "Use BRCMSTB UART for low-level debug"
290 UART physical and virtual address is automatically provided
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| /Linux-v6.1/Documentation/devicetree/bindings/dma/ |
| D | mediatek,uart-dma.yaml | 4 $id: http://devicetree.org/schemas/dma/mediatek,uart-dma.yaml#
7 title: MediaTek UART APDMA controller
13 The MediaTek UART APDMA controller provides DMA capabilities
14 for the UART peripheral bus.
24 - mediatek,mt2712-uart-dma
25 - mediatek,mt6795-uart-dma
26 - mediatek,mt8365-uart-dma
27 - mediatek,mt8516-uart-dma
28 - const: mediatek,mt6577-uart-dma
30 - mediatek,mt6577-uart-dma
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