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/Linux-v6.1/arch/m68k/include/asm/
Dmcfuart.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * mcfuart.h -- ColdFire internal UART support defines.
7 * (C) Copyright 1999-2003, Greg Ungerer (gerg@snapgear.com)
23 unsigned int uartclk; /* UART clock rate */
27 * Define the ColdFire UART register set addresses.
29 #define MCFUART_UMR 0x00 /* Mode register (r/w) */
31 #define MCFUART_UCSR 0x04 /* Clock Select (w) */
32 #define MCFUART_UCR 0x08 /* Command register (w) */
34 #define MCFUART_UTB 0x0c /* Transmit Buffer (w) */
36 #define MCFUART_UACR 0x10 /* Auxiliary Control (w) */
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DMC68328.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 /* include/asm-m68knommu/MC68328.h: '328 control registers
8 * Based on include/asm-m68knommu/MC68332.h
26 * 0xFFFFF0xx -- System Control
36 #define SCR_WDTH8 0x01 /* 8-Bit Width Select */
39 #define SCR_BETEN 0x10 /* Bus-Error Time-Out Enable */
42 #define SCR_BETO 0x80 /* Bus-Error TimeOut */
52 * 0xFFFFF1xx -- Chip-Select logic
58 * 0xFFFFF2xx -- Phase Locked Loop (PLL) & Power Control
76 #define GRPBASE_GBA_MASK 0xfff0 /* Group Base Address (bits 31-20) */
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DMC68VZ328.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 /* include/asm-m68knommu/MC68VZ328.h: 'VZ328 control registers
5 * Copyright (c) 2000-2001 Lineo Inc. <www.lineo.com>
6 * Copyright (c) 2000-2001 Lineo Canada Corp. <www.lineo.ca>
9 * Based on include/asm-m68knommu/MC68332.h
29 * 0xFFFFF0xx -- System Control
39 #define SCR_WDTH8 0x01 /* 8-Bit Width Select */
42 #define SCR_BETEN 0x10 /* Bus-Error Time-Out Enable */
45 #define SCR_BETO 0x80 /* Bus-Error TimeOut */
55 * 0xFFFFF1xx -- Chip-Select logic
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DMC68EZ328.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 /* include/asm-m68knommu/MC68EZ328.h: 'EZ328 control registers
8 * Based on include/asm-m68knommu/MC68332.h
27 * 0xFFFFF0xx -- System Control
37 #define SCR_WDTH8 0x01 /* 8-Bit Width Select */
40 #define SCR_BETEN 0x10 /* Bus-Error Time-Out Enable */
43 #define SCR_BETO 0x80 /* Bus-Error TimeOut */
53 * 0xFFFFF1xx -- Chip-Select logic
84 #define CSA_EN 0x0001 /* Chip-Select Enable */
85 #define CSA_SIZ_MASK 0x000e /* Chip-Select Size */
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/Linux-v6.1/drivers/extcon/
Dextcon-max8997.c1 // SPDX-License-Identifier: GPL-2.0+
3 // extcon-max8997.c - MAX8997 extcon driver to support MAX8997 MUIC
8 #include <linux/devm-helpers.h>
18 #include <linux/mfd/max8997-private.h>
19 #include <linux/extcon-provider.h>
22 #define DEV_NAME "max8997-muic"
39 { MAX8997_MUICIRQ_ADCError, "muic-ADCERROR" },
40 { MAX8997_MUICIRQ_ADCLow, "muic-ADCLOW" },
41 { MAX8997_MUICIRQ_ADC, "muic-ADC" },
42 { MAX8997_MUICIRQ_VBVolt, "muic-VBVOLT" },
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Dextcon-max14577.c1 // SPDX-License-Identifier: GPL-2.0+
3 // extcon-max14577.c - MAX14577/77836 extcon driver to support MUIC
9 #include <linux/devm-helpers.h>
16 #include <linux/mfd/max14577-private.h>
17 #include <linux/extcon-provider.h>
47 { MAX14577_IRQ_INT1_ADC, "muic-ADC" },
48 { MAX14577_IRQ_INT1_ADCLOW, "muic-ADCLOW" },
49 { MAX14577_IRQ_INT1_ADCERR, "muic-ADCError" },
50 { MAX14577_IRQ_INT2_CHGTYP, "muic-CHGTYP" },
51 { MAX14577_IRQ_INT2_CHGDETRUN, "muic-CHGDETRUN" },
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Dextcon-max77693.c1 // SPDX-License-Identifier: GPL-2.0+
3 // extcon-max77693.c - MAX77693 extcon driver to support MAX77693 MUIC
8 #include <linux/devm-helpers.h>
18 #include <linux/mfd/max77693-common.h>
19 #include <linux/mfd/max77693-private.h>
20 #include <linux/extcon-provider.h>
24 #define DEV_NAME "max77693-muic"
30 * extcon-max77693 driver use 'default_init_data' to bring up base operation
35 /* STATUS2 - [3]ChgDetRun */
39 /* INTMASK1 - Unmask [3]ADC1KM,[0]ADCM */
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/Linux-v6.1/drivers/tty/serial/
Dsunsab.c1 // SPDX-License-Identifier: GPL-2.0
11 * rates to be programmed into the UART. Also eliminated a lot of
13 * Theodore Ts'o <tytso@mit.edu>, 2001-Oct-12
15 * Ported to new 2.5.x UART layer.
49 struct uart_port port; /* Generic UART port */
51 unsigned long irqflags; /* IRQ state flags */
52 int dsr; /* Current DSR state */
74 * This assumes you have a 29.4912 MHz clock for your UART.
93 int timeout = up->tec_timeout; in sunsab_tec_wait()
95 while ((readb(&up->regs->r.star) & SAB82532_STAR_TEC) && --timeout) in sunsab_tec_wait()
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Darc_uart.c1 // SPDX-License-Identifier: GPL-2.0
3 * ARC On-Chip(fpga) UART Driver
5 * Copyright (C) 2010-2012 Synopsys, Inc. (www.synopsys.com)
8 * -Decoupled the driver from arch/arc
10 * +Using early_platform_xxx() for early console (thx to mach-shmobile/xxx)
13 * -Is uart_tx_stopped() not done in tty write path as it has already been
17 * -New Serial Core based ARC UART driver
18 * -Derived largely from blackfin driver albiet with some major tweaks
21 * -check if sysreq works
37 * ARC UART Hardware Specs
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/Linux-v6.1/drivers/tty/serial/jsm/
Djsm.h1 /* SPDX-License-Identifier: GPL-2.0+ */
49 dev_dbg(pdev->dev, fmt, ##__VA_ARGS__); \
76 /* Board State Definitions */
94 #define JSM_VERSION "jsm: 1.2-1-INKERNEL"
95 #define JSM_PARTNUM "40002438_A-INKERNEL"
124 * Per-board information
128 int boardnum; /* Board number: 0-32 */
151 u32 bd_uart_offset; /* Space between each UART */
173 #define CH_OPENING 0x0080 /* Port in fragile open state */
174 #define CH_CLOSING 0x0100 /* Port in fragile close state */
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/Linux-v6.1/Documentation/devicetree/bindings/pinctrl/
Dqcom,msm8909-tlmm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qcom,msm8909-tlmm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Stephan Gerhold <stephan@gerhold.net>
17 - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
21 const: qcom,msm8909-tlmm
27 interrupt-controller: true
28 '#interrupt-cells': true
29 gpio-controller: true
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Dqcom,sc8180x-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qcom,sc8180x-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
17 - $ref: "pinctrl.yaml#"
18 - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
22 const: qcom,sc8180x-tlmm
27 reg-names:
29 - const: "west"
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Dqcom,sm8350-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qcom,sm8350-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Vinod Koul <vkoul@kernel.org>
17 - $ref: "pinctrl.yaml#"
18 - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
22 const: qcom,sm8350-tlmm
28 interrupt-controller: true
29 '#interrupt-cells': true
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Dqcom,sm8450-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qcom,sm8450-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Vinod Koul <vkoul@kernel.org>
17 - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
21 const: qcom,sm8450-tlmm
27 interrupt-controller: true
28 '#interrupt-cells': true
29 gpio-controller: true
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Dqcom,sc8280xp-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qcom,sc8280xp-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
17 - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
21 const: qcom,sc8280xp-tlmm
27 interrupt-controller: true
28 '#interrupt-cells': true
29 gpio-controller: true
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Dqcom,sm6375-tlmm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qcom,sm6375-tlmm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Konrad Dybcio <konrad.dybcio@somainline.org>
17 - $ref: "pinctrl.yaml#"
18 - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
22 const: qcom,sm6375-tlmm
28 interrupt-controller: true
29 '#interrupt-cells': true
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Dqcom,sm6350-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qcom,sm6350-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Konrad Dybcio <konrad.dybcio@somainline.org>
17 - $ref: "pinctrl.yaml#"
18 - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
22 const: qcom,sm6350-tlmm
28 interrupt-controller: true
29 '#interrupt-cells': true
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Dqcom,sdx65-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qcom,sdx65-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Vamsi krishna Lanka <quic_vamslank@quicinc.com>
18 const: qcom,sdx65-tlmm
26 interrupt-controller: true
28 '#interrupt-cells':
30 include/dt-bindings/interrupt-controller/irq.h
33 gpio-controller: true
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/Linux-v6.1/include/linux/mfd/
Dmax8997.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * max8997.h - Driver for the Maxim 8997/8966
5 * Copyright (C) 2009-2010 Samsung Electrnoics
83 /* Check cable state after certain delay */
87 * Default usb/uart path whether UART/USB or AUX_UART/AUX_USB
88 * h/w path of COMP2/COMN1 on CONTROL1 register.
123 * [0 - 3]: valid pattern number
126 * [0 - 15]: available cycles
128 * [0 - 255]: available period
157 * [0 - 31]: MAX8997_FLASH_MODE and MAX8997_FLASH_PIN_CONTROL_MODE
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/Linux-v6.1/sound/pci/
Dens1370.c1 // SPDX-License-Identifier: GPL-2.0-or-later
8 /* Power-Management-Code ( CONFIG_PM )
11 * using https://www.kernel.org/doc/html/latest/sound/kernel-api/writing-an-alsa-driver.html
64 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
96 MODULE_PARM_DESC(spdif, "S/PDIF output (-1 = none, 0 = auto, 1 = force).");
111 #define CT5880REV_CT5880_D 0x03 /* ??? -jk */
121 #define ES_REG(ensoniq, x) ((ensoniq)->port + ES_REG_##x)
123 #define ES_REG_CONTROL 0x00 /* R/W: Interrupt/Chip select control register */
135 #define ES_1371_GPIO_IN(i) (((i)>>20)&0x0f)/* GPIO in [3:0] pins - R/O */
139 #define ES_1371_GPIO_OUT(o) (((o)&0x0f)<<16)/* GPIO out [3:0] pins - W/R */
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/Linux-v6.1/include/linux/
Dserial_core.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
24 ((port)->cons && (port)->cons->index == (port)->line)
35 * struct uart_ops -- interface between serial_core and the driver
53 * This function sets the modem control lines for @port to the state
56 * - %TIOCM_RTS RTS signal.
57 * - %TIOCM_DTR DTR signal.
58 * - %TIOCM_OUT1 OUT1 signal.
59 * - %TIOCM_OUT2 OUT2 signal.
60 * - %TIOCM_LOOP Set the port into loopback mode.
66 * Locking: @port->lock taken.
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/Linux-v6.1/drivers/usb/serial/
Dio_16654.h1 /* SPDX-License-Identifier: GPL-2.0+ */
4 * 16654.H Definitions for 16C654 UART used on EdgePorts
20 // UART register numbers
21 // Numbers 0-7 are passed to the Edgeport directly. Numbers 8 and
27 // the EdgePort firmware -- that includes THR, RHR, IER, FCR.
44 #define XON1 12 // Bank2[ 4 ] Xon-1
45 #define XON2 13 // Bank2[ 5 ] Xon-2
46 #define XOFF1 14 // Bank2[ 6 ] Xoff-1
47 #define XOFF2 15 // Bank2[ 7 ] Xoff-2
62 #define IER_XOFF 0x20 // Enable s/w flow control (XOFF) interrupt
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/Linux-v6.1/drivers/misc/ti-st/
Dst_kim.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Copyright (C) 2009-2010 Texas Instruments
27 #define MAX_ST_DEVICES 3 /* Imagine 1 on each UART for now */
34 * st_get_plat_device -
47 * validate_firmware_response -
54 struct sk_buff *skb = kim_gdata->rx_skb; in validate_firmware_response()
63 if (skb->data[2] == 0x01 && skb->data[3] == 0x01 && in validate_firmware_response()
64 skb->data[4] == 0x10 && skb->data[5] == 0x00) { in validate_firmware_response()
66 memcpy(kim_gdata->resp_buffer, in validate_firmware_response()
67 kim_gdata->rx_skb->data, in validate_firmware_response()
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/Linux-v6.1/drivers/soc/samsung/
Dexynos-usi.c1 // SPDX-License-Identifier: GPL-2.0
17 #include <dt-bindings/soc/samsung,exynos-usi.h>
41 enum exynos_usi_ver ver; /* USI IP-core version */
71 [USI_V2_UART] = { .name = "uart", .val = USI_V2_SW_CONF_UART },
88 .compatible = "samsung,exynos850-usi",
96 * exynos_usi_set_sw_conf - Set USI block configuration mode
100 * Select underlying serial protocol (UART/SPI/I2C) in USI IP-core.
109 if (mode < usi->data->min_mode || mode > usi->data->max_mode) in exynos_usi_set_sw_conf()
110 return -EINVAL; in exynos_usi_set_sw_conf()
113 ret = regmap_update_bits(usi->sysreg, usi->sw_conf, in exynos_usi_set_sw_conf()
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/Linux-v6.1/drivers/tty/serial/8250/
D8250_omap.c1 // SPDX-License-Identifier: GPL-2.0
3 * 8250-core based driver for the OMAP internal UART
5 * based on omap-serial.c, Copyright (C) 2010 Texas Instruments.
29 #include <linux/dma-mapping.h>
157 return readl(up->port.membase + (reg << up->port.regshift)); in uart_read()
167 struct omap8250_priv *priv = up->port.private_data; in __omap8250_set_mctrl()
172 if (!mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_RTS)) { in __omap8250_set_mctrl()
179 if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS)) in __omap8250_set_mctrl()
180 priv->efr |= UART_EFR_RTS; in __omap8250_set_mctrl()
182 priv->efr &= ~UART_EFR_RTS; in __omap8250_set_mctrl()
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