| /Linux-v5.10/drivers/net/ethernet/stmicro/stmmac/ |
| D | dwmac-sunxi.c | 23 struct clk *tx_clk; member
48 clk_set_rate(gmac->tx_clk, SUN7I_GMAC_GMII_RGMII_RATE); in sun7i_gmac_init()
49 clk_prepare_enable(gmac->tx_clk); in sun7i_gmac_init()
52 clk_set_rate(gmac->tx_clk, SUN7I_GMAC_MII_RATE); in sun7i_gmac_init()
53 ret = clk_prepare(gmac->tx_clk); in sun7i_gmac_init()
66 clk_disable(gmac->tx_clk); in sun7i_gmac_exit()
69 clk_unprepare(gmac->tx_clk); in sun7i_gmac_exit()
84 clk_disable(gmac->tx_clk); in sun7i_fix_speed()
87 clk_unprepare(gmac->tx_clk); in sun7i_fix_speed()
90 clk_set_rate(gmac->tx_clk, SUN7I_GMAC_GMII_RGMII_RATE); in sun7i_fix_speed()
[all …]
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| D | dwmac-intel-plat.c | 20 struct clk *tx_clk; member
37 rate = clk_get_rate(dwmac->tx_clk); in kmb_eth_fix_mac_speed()
57 ret = clk_set_rate(dwmac->tx_clk, rate); in kmb_eth_fix_mac_speed()
104 dwmac->tx_clk = NULL; in intel_eth_plat_probe()
115 dwmac->tx_clk = devm_clk_get(&pdev->dev, "tx_clk"); in intel_eth_plat_probe()
116 if (IS_ERR(dwmac->tx_clk)) { in intel_eth_plat_probe()
117 ret = PTR_ERR(dwmac->tx_clk); in intel_eth_plat_probe()
121 clk_prepare_enable(dwmac->tx_clk); in intel_eth_plat_probe()
124 rate = clk_get_rate(dwmac->tx_clk); in intel_eth_plat_probe()
128 ret = clk_set_rate(dwmac->tx_clk, rate); in intel_eth_plat_probe()
[all …]
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| D | dwmac-sun8i.c | 60 * @tx_clk: reference to MAC TX clock
70 struct clk *tx_clk; member
555 ret = clk_prepare_enable(gmac->tx_clk); in sun8i_dwmac_init()
1018 clk_disable_unprepare(gmac->tx_clk); in sun8i_dwmac_exit()
1151 gmac->tx_clk = devm_clk_get(dev, "stmmaceth"); in sun8i_dwmac_probe()
1152 if (IS_ERR(gmac->tx_clk)) { in sun8i_dwmac_probe()
1154 return PTR_ERR(gmac->tx_clk); in sun8i_dwmac_probe()
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| D | dwmac-meson8b.c | 357 /* enable TX_CLK and PHY_REF_CLK generator */ in meson8b_init_prg_eth()
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| /Linux-v5.10/arch/arm64/boot/dts/xilinx/ |
| D | zynqmp-clk-ccf.dtsi | 123 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
130 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
137 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
144 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
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| D | zynqmp.dtsi | 447 clock-names = "pclk", "hclk", "tx_clk";
459 clock-names = "pclk", "hclk", "tx_clk";
471 clock-names = "pclk", "hclk", "tx_clk";
483 clock-names = "pclk", "hclk", "tx_clk";
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| /Linux-v5.10/Documentation/devicetree/bindings/net/ |
| D | macb.txt | 27 Optional elements: 'tx_clk'
49 clock-names = "pclk", "hclk", "tx_clk";
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| D | qcom-emac.txt | 44 "mdio_clk", "tx_clk", "rx_clk", "sys_clk";
93 "mdio_clk", "tx_clk", "rx_clk", "sys_clk";
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| D | intel,dwmac-plat.yaml | 42 - const: tx_clk
110 clock-names = "stmmaceth", "ptp_ref", "tx_clk";
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| /Linux-v5.10/drivers/net/phy/ |
| D | micrel.c | 529 /* set tx to -0.42ns and tx_clk to +0.96ns to get 1.38ns delay */
533 /* set tx and tx_clk to "No delay adjustment" to keep 0ns
615 u16 rx, tx, rx_clk, tx_clk; in ksz9031_config_rgmii_delay() local
621 tx_clk = TX_CLK_ND; in ksz9031_config_rgmii_delay()
627 tx_clk = TX_CLK_ID; in ksz9031_config_rgmii_delay()
633 tx_clk = TX_CLK_ND; in ksz9031_config_rgmii_delay()
639 tx_clk = TX_CLK_ID; in ksz9031_config_rgmii_delay()
670 FIELD_PREP(MII_KSZ9031RN_GTX_CLK, tx_clk) | in ksz9031_config_rgmii_delay()
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| D | icplus.c | 36 #define IP1001_TXPHASE_SEL BIT(1) /* Add delay on TX_CLK */
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| /Linux-v5.10/drivers/dma/xilinx/ |
| D | xilinx_dma.c | 470 struct clk **tx_clk, struct clk **txs_clk,
487 * @tx_clk: DMA mm2s clock
505 struct clk *tx_clk; member
2550 struct clk **tx_clk, struct clk **rx_clk, in axidma_clk_init() argument
2561 *tx_clk = devm_clk_get(&pdev->dev, "m_axi_mm2s_aclk"); in axidma_clk_init()
2562 if (IS_ERR(*tx_clk)) in axidma_clk_init()
2563 *tx_clk = NULL; in axidma_clk_init()
2579 err = clk_prepare_enable(*tx_clk); in axidma_clk_init()
2581 dev_err(&pdev->dev, "failed to enable tx_clk (%d)\n", err); in axidma_clk_init()
2602 clk_disable_unprepare(*tx_clk); in axidma_clk_init()
[all …]
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| /Linux-v5.10/drivers/net/ethernet/cadence/ |
| D | macb_main.c | 499 netdev_err(dev, "adjusting tx_clk failed.\n"); in macb_set_tx_clk()
652 macb_set_tx_clk(bp->tx_clk, speed, ndev); in macb_mac_link_up()
3569 struct clk **hclk, struct clk **tx_clk, in macb_clk_init() argument
3602 *tx_clk = devm_clk_get_optional(&pdev->dev, "tx_clk"); in macb_clk_init()
3603 if (IS_ERR(*tx_clk)) in macb_clk_init()
3604 return PTR_ERR(*tx_clk); in macb_clk_init()
3626 err = clk_prepare_enable(*tx_clk); in macb_clk_init()
3628 dev_err(&pdev->dev, "failed to enable tx_clk (%d)\n", err); in macb_clk_init()
3650 clk_disable_unprepare(*tx_clk); in macb_clk_init()
4178 struct clk **hclk, struct clk **tx_clk, in at91ether_clk_init() argument
[all …]
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| D | macb.h | 1111 struct clk **hclk, struct clk **tx_clk,
1190 struct clk *tx_clk; member
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| /Linux-v5.10/drivers/net/dsa/sja1105/ |
| D | sja1105_clocking.c | 280 /* Per MII spec, the PHY (which is us) drives the TX_CLK pin */ in sja1105_mii_clocking_setup()
382 pad_mii_tx.clk_os = 3; /* TX_CLK output stage */ in sja1105_rgmii_cfg_pad_tx_config()
383 pad_mii_tx.clk_ih = 0; /* TX_CLK input hysteresis (default) */ in sja1105_rgmii_cfg_pad_tx_config()
384 pad_mii_tx.clk_ipud = 2; /* TX_CLK input stage (default) */ in sja1105_rgmii_cfg_pad_tx_config()
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| /Linux-v5.10/arch/powerpc/boot/dts/ |
| D | mpc832x_rdb.dts | 180 3 23 2 0 1 0 /* TX_CLK (CLK3) */
200 3 24 2 0 1 0 /* TX_CLK (CLK10) */
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| D | mpc832x_mds.dts | 192 3 24 2 0 1 0 /* TX_CLK (CLK10) */
212 3 6 2 0 1 0 /* TX_CLK (CLK8) */
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| /Linux-v5.10/arch/arm/boot/dts/ |
| D | socfpga_arria10_socdk.dtsi | 75 * for TX_CLK on Arria 10.
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| D | zynq-7000.dtsi | 239 clock-names = "pclk", "hclk", "tx_clk";
250 clock-names = "pclk", "hclk", "tx_clk";
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| /Linux-v5.10/drivers/net/ethernet/intel/e1000/ |
| D | e1000_ethtool.c | 1116 /* Because we reset the PHY above, we need to re-force TX_CLK in the in e1000_phy_reset_clk_and_crs()
1162 /* Have to setup TX_CLK and TX_CRS after software reset */ in e1000_nonintegrated_phy_loopback()
1170 /* Have to setup TX_CLK and TX_CRS after software reset */ in e1000_nonintegrated_phy_loopback()
1181 /* Setup TX_CLK and TX_CRS one more time. */ in e1000_nonintegrated_phy_loopback()
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| D | e1000_hw.h | 2771 #define M88E1000_EPSCR_TX_CLK_2_5 0x0060 /* 2.5 MHz TX_CLK */
2772 #define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */
2773 #define M88E1000_EPSCR_TX_CLK_0 0x0000 /* NO TX_CLK */
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| /Linux-v5.10/drivers/net/ethernet/qualcomm/emac/ |
| D | emac.c | 69 "axi_clk", "cfg_ahb_clk", "high_speed_clk", "mdio_clk", "tx_clk",
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| /Linux-v5.10/drivers/net/ethernet/intel/igb/ |
| D | e1000_phy.c | 580 /* Force TX_CLK in the Extended PHY Specific Control Register in igb_copper_link_setup_m88()
1193 * After reset, TX_CLK and CRS on TX must be set. Return successful upon
1296 /* Resetting the phy means we need to re-force TX_CLK in the in igb_phy_force_speed_duplex_m88()
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| /Linux-v5.10/drivers/net/ethernet/intel/e1000e/ |
| D | phy.c | 755 /* Force TX_CLK in the Extended PHY Specific Control Register in e1000e_copper_link_setup_m88()
1242 * After reset, TX_CLK and CRS on Tx must be set. Return successful upon
1322 /* Resetting the phy means we need to re-force TX_CLK in the in e1000e_phy_force_speed_duplex_m88()
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| D | defines.h | 752 #define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */
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