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/Linux-v6.1/drivers/net/ethernet/stmicro/stmmac/
Ddwmac-meson8b.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/clk.h>
10 #include <linux/clk-provider.h>
35 /* TX clock delay in ns = "8ns / 4 * tx_dly_val" (where 8ns are exactly one
36 * cycle of the 125MHz RGMII TX clock):
57 * the automatically delay and skew automatically (internally).
60 /* An internal counter based on the "timing-adjustment" clock. The counter is
62 * delay (= the counter value) when to start sampling RXEN and RXD[3:0].
66 * large input delay, the bit for that signal (RXEN = bit 0, RXD[3] = bit 1,
67 * ...) can be configured to be 1 to compensate for a delay of about 1ns.
[all …]
Ddwmac-mediatek.c1 // SPDX-License-Identifier: GPL-2.0
79 struct clk *rmii_internal_clk;
115 int rmii_clk_from_mac = plat->rmii_clk_from_mac ? RMII_CLK_SRC_INTERNAL : 0; in mt2712_set_interface()
116 int rmii_rxc = plat->rmii_rxc ? RMII_CLK_SRC_RXC : 0; in mt2712_set_interface()
120 switch (plat->phy_mode) { in mt2712_set_interface()
134 dev_err(plat->dev, "phy interface not supported\n"); in mt2712_set_interface()
135 return -EINVAL; in mt2712_set_interface()
138 regmap_write(plat->peri_regmap, PERI_ETH_PHY_INTF_SEL, intf_val); in mt2712_set_interface()
145 struct mac_delay_struct *mac_delay = &plat->mac_delay; in mt2712_delay_ps2stage()
147 switch (plat->phy_mode) { in mt2712_delay_ps2stage()
[all …]
Ddwmac-ingenic.c1 // SPDX-License-Identifier: GPL-2.0
3 * dwmac-ingenic.c - Ingenic SoCs DWMAC specific glue layer
9 #include <linux/clk.h>
76 struct ingenic_mac *mac = plat_dat->bsp_priv; in ingenic_mac_init()
79 if (mac->soc_info->set_mode) { in ingenic_mac_init()
80 ret = mac->soc_info->set_mode(plat_dat); in ingenic_mac_init()
90 struct ingenic_mac *mac = plat_dat->bsp_priv; in jz4775_mac_set_mode()
93 switch (plat_dat->interface) { in jz4775_mac_set_mode()
97 dev_dbg(mac->dev, "MAC PHY Control Register: PHY_INTERFACE_MODE_MII\n"); in jz4775_mac_set_mode()
103 dev_dbg(mac->dev, "MAC PHY Control Register: PHY_INTERFACE_MODE_GMII\n"); in jz4775_mac_set_mode()
[all …]
Ddwmac-sun8i.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * dwmac-sun8i.c - Allwinner sun8i DWMAC specific glue layer
8 #include <linux/clk.h>
11 #include <linux/mdio-mux.h>
27 /* General notes on dwmac-sun8i:
32 /* struct emac_variant - Describe dwmac-sun8i hardware variant
43 * @rx_delay_max: Maximum raw value for RX delay chain
44 * @tx_delay_max: Maximum raw value for TX delay chain
46 * the RX and TX delay chain registers. A
60 /* struct sunxi_priv_data - hold all sunxi private data
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/Linux-v6.1/Documentation/devicetree/bindings/net/dsa/
Dnxp,sja1105.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The SJA1105 SPI interface requires a CS-to-CLK time (t2 in UM10944.pdf) of at
16 - $ref: "dsa.yaml#"
17 - $ref: /schemas/spi/spi-peripheral-props.yaml#
20 - Vladimir Oltean <vladimir.oltean@nxp.com>
25 - nxp,sja1105e
26 - nxp,sja1105t
27 - nxp,sja1105p
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/Linux-v6.1/Documentation/devicetree/bindings/net/
Dti,dp83869.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
11 - $ref: "ethernet-phy.yaml#"
14 - Andrew Davis <afd@ti.com>
17 The DP83869HM device is a robust, fully-featured Gigabit (PHY) transceiver
18 with integrated PMD sublayers that supports 10BASE-Te, 100BASE-TX and
19 1000BASE-T Ethernet protocols. The DP83869 also supports 1000BASE-X and
20 100BASE-FX Fiber protocols.
23 the DP83869HM can run 1000BASE-X-to-1000BASE-T and 100BASE-FX-to-100BASE-TX
[all …]
Dmediatek-dwmac.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/mediatek-dwmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Biao Huang <biao.huang@mediatek.com>
21 - mediatek,mt2712-gmac
22 - mediatek,mt8188-gmac
23 - mediatek,mt8195-gmac
25 - compatible
28 - $ref: "snps,dwmac.yaml#"
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Dingenic,mac.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
18 - ingenic,jz4775-mac
19 - ingenic,x1000-mac
20 - ingenic,x1600-mac
21 - ingenic,x1830-mac
22 - ingenic,x2000-mac
30 interrupt-names:
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Dsnps,dwmac.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexandre Torgue <alexandre.torgue@foss.st.com>
11 - Giuseppe Cavallaro <peppe.cavallaro@st.com>
12 - Jose Abreu <joabreu@synopsys.com>
23 - snps,dwmac
24 - snps,dwmac-3.40a
25 - snps,dwmac-3.50a
26 - snps,dwmac-3.610
[all …]
/Linux-v6.1/drivers/net/phy/
Dmicrel.c1 // SPDX-License-Identifier: GPL-2.0+
9 * Copyright (c) 2010-2013 Micrel, Inc.
29 #include <linux/clk.h>
30 #include <linux/delay.h>
119 * The value is calculated as following: (1/1000000)/((2^-32)/4)
393 const struct kszphy_type *type = phydev->drv->driver_data; in kszphy_config_intr()
397 if (type && type->interrupt_level_mask) in kszphy_config_intr()
398 mask = type->interrupt_level_mask; in kszphy_config_intr()
410 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { in kszphy_config_intr()
475 return -EINVAL; in kszphy_setup_led()
[all …]
/Linux-v6.1/drivers/input/serio/
Dps2-gpio.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * GPIO based serio bus driver for bit banging the PS/2 protocol
5 * Author: Danilo Krummrich <danilokrummrich@dk-develop.de>
21 #include <linux/delay.h>
24 #define DRIVER_NAME "ps2-gpio"
50 * interrupt interval should be ~60us. Let's allow +/- 20us for frequency
61 * |-----------------| |--------|
68 #define PS2_IRQ_MIN_INTERVAL_US (PS2_CLK_MIN_INTERVAL_US - 20)
93 } tx; member
98 struct ps2_gpio_data *drvdata = serio->port_data; in ps2_gpio_open()
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/Linux-v6.1/arch/arm/boot/dts/
Dstm32mp15xx-dhcor-avenger96.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
3 * Copyright (C) Linaro Ltd 2019 - All Rights Reserved
9 #include "stm32mp15xx-dhcor-io1v8.dtsi"
22 cec_clock: clk-cec-fixed {
23 #clock-cells = <0>;
24 compatible = "fixed-clock";
25 clock-frequency = <24000000>;
29 stdout-path = "serial0:115200n8";
32 hdmi-out {
33 compatible = "hdmi-connector";
[all …]
Dam335x-nano.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013 Newflow Ltd - http://www.newflow.co.uk/
5 /dts-v1/;
15 cpu0-supply = <&dcdc2_reg>;
25 compatible = "gpio-leds";
30 default-state = "off";
36 pinctrl-names = "default";
37 pinctrl-0 = <&misc_pins>;
40 pinctrl-single,pins = <
46 pinctrl-single,pins = <
[all …]
Dam335x-evm.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
5 /dts-v1/;
8 #include <dt-bindings/interrupt-controller/irq.h>
12 compatible = "ti,am335x-evm", "ti,am33xx";
16 cpu0-supply = <&vdd1_reg>;
26 stdout-path = &uart0;
30 compatible = "regulator-fixed";
31 regulator-name = "vbat";
32 regulator-min-microvolt = <5000000>;
[all …]
Dam335x-cm-t335.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * am335x-cm-t335.dts - Device Tree file for Compulab CM-T335
5 * Copyright (C) 2014 - 2015 CompuLab Ltd. - http://www.compulab.co.il/
8 /dts-v1/;
11 #include <dt-bindings/interrupt-controller/irq.h>
14 model = "CompuLab CM-T335";
15 compatible = "compulab,cm-t335", "ti,am33xx";
23 compatible = "gpio-leds";
24 pinctrl-names = "default";
25 pinctrl-0 = <&gpio_led_pins>;
[all …]
Dam335x-baltos.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
12 #include <dt-bindings/pwm/pwm.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
20 cpu0-supply = <&vdd1_reg>;
30 compatible = "regulator-fixed";
31 regulator-name = "vbat";
32 regulator-min-microvolt = <5000000>;
33 regulator-max-microvolt = <5000000>;
34 regulator-boot-on;
[all …]
/Linux-v6.1/drivers/net/ethernet/marvell/
Dmvneta.c7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
14 #include <linux/clk.h>
156 #define MVNETA_TX_INTR_MASK(nr_txqs) (((1 << nr_txqs) - 1) << 0)
158 #define MVNETA_RX_INTR_MASK(nr_rxqs) (((1 << nr_rxqs) - 1) << 8)
270 * to cover all rate-limit values from 10Kbps up to 5Gbps
296 (((index) < (q)->last_desc) ? ((index) + 1) : 0)
339 /* Max number of Tx descriptors */
365 #define MVNETA_MAX_RX_BUF_SIZE (PAGE_SIZE - MVNETA_SKB_PAD)
368 ((addr >= txq->tso_hdrs_phys) && \
369 (addr < txq->tso_hdrs_phys + txq->size * TSO_HEADER_SIZE))
[all …]
/Linux-v6.1/arch/arm64/boot/dts/freescale/
Dimx8mm-venice-gw7903.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/linux-event-codes.h>
10 #include <dt-bindings/leds/common.h>
11 #include <dt-bindings/phy/phy-imx8-pcie.h>
17 compatible = "gw,imx8mm-gw7903", "fsl,imx8mm";
25 stdout-path = &uart2;
33 gpio-keys {
34 compatible = "gpio-keys";
[all …]
/Linux-v6.1/arch/arm64/boot/dts/xilinx/
Dzynqmp-zcu102-revA.dts1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2015 - 2021, Xilinx, Inc.
10 /dts-v1/;
13 #include "zynqmp-clk-ccf.dtsi"
14 #include <dt-bindings/input/input.h>
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
17 #include <dt-bindings/phy/phy.h>
21 compatible = "xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
39 stdout-path = "serial0:115200n8";
[all …]
Dzynqmp-zcu111-revA.dts1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2017 - 2021, Xilinx, Inc.
10 /dts-v1/;
13 #include "zynqmp-clk-ccf.dtsi"
14 #include <dt-bindings/input/input.h>
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
17 #include <dt-bindings/phy/phy.h>
21 compatible = "xlnx,zynqmp-zcu111-revA", "xlnx,zynqmp-zcu111", "xlnx,zynqmp";
38 stdout-path = "serial0:115200n8";
[all …]
Dzynqmp-zcu106-revA.dts1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2016 - 2021, Xilinx, Inc.
10 /dts-v1/;
13 #include "zynqmp-clk-ccf.dtsi"
14 #include <dt-bindings/input/input.h>
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
17 #include <dt-bindings/phy/phy.h>
21 compatible = "xlnx,zynqmp-zcu106-revA", "xlnx,zynqmp-zcu106", "xlnx,zynqmp";
39 stdout-path = "serial0:115200n8";
[all …]
/Linux-v6.1/arch/arm64/boot/dts/renesas/
Dulcb.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the R-Car Gen3 ULCB board
10 * SSI-AK4613
11 * aplay -D plughw:0,0 xxx.wav
12 * arecord -D plughw:0,0 xxx.wav
13 * SSI-HDMI
14 * aplay -D plughw:0,1 xxx.wav
17 #include <dt-bindings/gpio/gpio.h>
18 #include <dt-bindings/input/input.h>
21 model = "Renesas R-Car Gen3 ULCB board";
[all …]
Dr8a77970.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the R-Car V3M (R8A77970) SoC
5 * Copyright (C) 2016-2017 Renesas Electronics Corp.
9 #include <dt-bindings/clock/r8a77970-cpg-mssr.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/power/r8a77970-sysc.h>
16 #address-cells = <2>;
17 #size-cells = <2>;
19 /* External CAN clock - to be overridden by boards that provide it */
[all …]
/Linux-v6.1/drivers/phy/amlogic/
Dphy-meson-axg-mipi-dphy.c1 // SPDX-License-Identifier: GPL-2.0
13 #include <linux/clk.h>
14 #include <linux/delay.h>
33 * [11] mipi divider clk selection.
52 /* [31] clk lane tx_hs_en control selection.
53 * 1: from register. 0: use clk lane state machine.
55 * [29] clk lane tx_lp_en contrl selection.
56 * 1: from register. 0: from clk lane state machine.
88 * [4] clk chan power down. this bit is also used as the power down
101 * [20:17] clk lane state. {mbias_ready, tx_stop, tx_ulps, tx_hs_active}
[all …]
/Linux-v6.1/drivers/spi/
Dspi-atmel.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/clk.h>
12 #include <linux/delay.h>
13 #include <linux/dma-mapping.h>
216 (((value) & ((1 << SPI_##name##_SIZE) - 1)) << SPI_##name##_OFFSET)
218 (((value) >> SPI_##name##_OFFSET) & ((1 << SPI_##name##_SIZE) - 1))
220 (((old) & ~(((1 << SPI_##name##_SIZE) - 1) << SPI_##name##_OFFSET)) \
225 readl_relaxed((port)->regs + SPI_##reg)
227 writel_relaxed((value), (port)->regs + SPI_##reg)
229 writew_relaxed((value), (port)->regs + SPI_##reg)
[all …]

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