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/Linux-v5.15/Documentation/devicetree/bindings/media/
Dvideo-interfaces.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/video-interfaces.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sakari Ailus <sakari.ailus@linux.intel.com>
11 - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
29 #address-cells = <1>;
30 #size-cells = <0>;
45 a common scheme using '#address-cells', '#size-cells' and 'reg' properties is
49 specify #address-cells, #size-cells properties independently for the 'port'
[all …]
Dti,omap3isp.txt4 The DT definitions can be found in include/dt-bindings/media/omap3-isp.h.
9 compatible : must contain "ti,omap3-isp"
11 reg : the two registers sets (physical address and length) for the
17 syscon : the phandle and register offset to the Complex I/O or CSI-PHY
19 ti,phy-type : 0 -- OMAP3ISP_PHY_TYPE_COMPLEX_IO (e.g. 3430)
20 1 -- OMAP3ISP_PHY_TYPE_CSIPHY (e.g. 3630)
21 #clock-cells : Must be 1 --- the ISP provides two external clocks,
24 clock bindings in ../clock/clock-bindings.txt.
27 ---------------------
30 video-interfaces.txt in the same directory.
[all …]
Dsamsung-s5c73m3.txt2 ------------------------------
4 The S5C73M3 camera ISP supports MIPI CSI-2 and parallel (ITU-R BT.656) video
6 is used, mostly for transferring the firmware to and from the device. Two
11 ---------------------
15 - compatible : "samsung,s5c73m3";
16 - reg : I2C slave address of the sensor;
17 - vdd-int-supply : digital power supply (1.2V);
18 - vdda-supply : analog power supply (1.2V);
19 - vdd-reg-supply : regulator input power supply (2.8V);
20 - vddio-host-supply : host I/O power supply (1.8V to 2.8V);
[all …]
/Linux-v5.15/Documentation/devicetree/bindings/media/i2c/
Dimx219.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Sony 1/4.0-Inch 8Mpixel CMOS Digital Image Sensor
10 - Dave Stevenson <dave.stevenson@raspberrypi.com>
12 description: |-
13 The Sony imx219 is a 1/4.0-inch CMOS active pixel digital image sensor
16 Image data is sent through MIPI CSI-2, which is configured as either 2 or
30 VDIG-supply:
34 VANA-supply:
[all …]
Dst,st-mipid02.txt1 STMicroelectronics MIPID02 CSI-2 to PARALLEL bridge
3 MIPID02 has two CSI-2 input ports, only one of those ports can be active at a
4 time. Active port input stream will be de-serialized and its content outputted
6 CSI-2 first input port is a dual lane 800Mbps per lane whereas CSI-2 second
7 input port is a single lane 800Mbps. Both ports support clock and data lane
8 polarity swap. First port also supports data lane swap.
11 YUV420 8-bit, YUV422 8-bit and YUV420 10-bit.
14 - compatible: shall be "st,st-mipid02"
15 - clocks: reference to the xclk input clock.
16 - clock-names: shall be "xclk".
[all …]
Dtc358743.txt1 * Toshiba TC358743 HDMI-RX to MIPI CSI2-TX Bridge
3 The Toshiba TC358743 HDMI-RX to MIPI CSI2-TX (H2C) is a bridge that converts
4 a HDMI stream to MIPI CSI-2 TX. It is programmable through I2C.
8 - compatible: value should be "toshiba,tc358743"
9 - clocks, clock-names: should contain a phandle link to the reference clock
14 - reset-gpios: gpio phandle GPIO connected to the reset pin
15 - interrupts: GPIO connected to the interrupt pin
16 - data-lanes: should be <1 2 3 4> for four-lane operation,
17 or <1 2> for two-lane operation
18 - clock-lanes: should be <0>
[all …]
Dadv748x.txt4 HDMI receiver. They can output CSI-2 on two independent outputs TXA and TXB
9 - compatible: Must contain one of the following
10 - "adi,adv7481" for the ADV7481
11 - "adi,adv7482" for the ADV7482
13 - reg: I2C slave addresses
14 The ADV748x has up to twelve 256-byte maps that can be accessed via the
21 - interrupt-names: Should specify the interrupts as "intrq1", "intrq2" and/or
24 - interrupts: Specify the interrupt lines for the ADV748x
25 - reg-names : Names of maps with programmable addresses.
26 It shall contain all maps needing a non-default address.
[all …]
Dov8856.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Dongchun Zhu <dongchun.zhu@mediatek.com>
13 description: |-
14 The Omnivision OV8856 is a high performance, 1/4-inch, 8 megapixel, CMOS
15 image sensor that delivers 3264x2448 at 30fps. It provides full-frame,
16 sub-sampled, and windowed 10-bit MIPI images in various formats via the
18 through I2C and two-wire SCCB. The sensor output is available via CSI-2
19 serial data output (up to 4-lane).
[all …]
Dov5640.txt1 * Omnivision OV5640 MIPI CSI-2 / parallel sensor
4 - compatible: should be "ovti,ov5640"
5 - clocks: reference to the xclk input clock.
6 - clock-names: should be "xclk".
7 - DOVDD-supply: Digital I/O voltage supply, 1.8 volts
8 - AVDD-supply: Analog voltage supply, 2.8 volts
9 - DVDD-supply: Digital core voltage supply, 1.5 volts
12 - reset-gpios: reference to the GPIO connected to the reset pin, if any.
14 - powerdown-gpios: reference to the GPIO connected to the powerdown pin,
16 - rotation: as defined in
[all …]
/Linux-v5.15/include/linux/platform_data/media/
Domap4iss.h1 /* SPDX-License-Identifier: GPL-2.0 */
15 * struct iss_csiphy_lane: CSI2 lane position and polarity
16 * @pos: position of the lane
17 * @pol: polarity of the lane
28 * struct iss_csiphy_lanes_cfg - CSI2 lane configuration
29 * @data: Configuration of one or two data lanes
30 * @clk: Clock lane configuration
38 * struct iss_csi2_platform_data - CSI2 interface platform data
/Linux-v5.15/Documentation/driver-api/nvdimm/
Dbtt.rst2 BTT - Block Translation Table
14 using stored energy in capacitors to complete in-flight block writes, or perhaps
15 in firmware. We don't have this luxury with persistent memory - if a write is in
23 the heart of it, is an indirection table that re-maps all the blocks on the
37 next arena). The following depicts the "On-disk" metadata layout::
40 Backing Store +-------> Arena
41 +---------------+ | +------------------+
43 | Arena 0 +---+ | 4K |
44 | 512G | +------------------+
46 +---------------+ | |
[all …]
/Linux-v5.15/drivers/media/platform/omap3isp/
Domap3isp.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * TI OMAP3 ISP - Bus Configuration
25 * struct isp_parallel_cfg - Parallel interface configuration
26 * @data_lane_shift: Data lane shifter
27 * 0 - CAMEXT[13:0] -> CAM[13:0]
28 * 2 - CAMEXT[13:2] -> CAM[11:0]
29 * 4 - CAMEXT[13:4] -> CAM[9:0]
30 * 6 - CAMEXT[13:6] -> CAM[7:0]
32 * 0 - Sample on rising edge, 1 - Sample on falling edge
34 * 0 - Active high, 1 - Active low
[all …]
/Linux-v5.15/drivers/gpu/drm/i915/display/
Dintel_dpio_phy.c2 * Copyright © 2014-2016 Intel Corporation
40 * IOSF-SB port.
42 * Each display PHY is made up of one or two channels. Each channel
43 * houses a common lane part which contains the PLL and other common
44 * logic. CH0 common lane also contains the IOSF-SB logic for the
53 * Eeach channel also has two splines (also called data lanes), and
54 * each spline is made up of one Physical Access Coding Sub-Layer
55 * (PCS) block and two TX lanes. So each channel has two PCS blocks
59 * Additionally the PHY also contains an AUX lane with AUX blocks
65 * Generally on VLV/CHV the common lane corresponds to the pipe and
[all …]
/Linux-v5.15/arch/arm/boot/dts/
Darmada-xp-mv78460.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
13 #include "armada-xp.dtsi"
17 compatible = "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
27 #address-cells = <1>;
28 #size-cells = <0>;
29 enable-method = "marvell,armada-xp-smp";
33 compatible = "marvell,sheeva-v7";
36 clock-latency = <1000000>;
41 compatible = "marvell,sheeva-v7";
[all …]
Darmada-395-gp.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
10 /dts-v1/;
11 #include "armada-395.dtsi"
15 compatible = "marvell,a395-gp", "marvell,armada395",
19 stdout-path = "serial0:115200n8";
31 internal-regs {
34 clock-frequency = <100000>;
62 clock-frequency = <200000000>;
63 broken-cd;
64 wp-inverted;
[all …]
Darmada-xp-mv78260.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
13 #include "armada-xp.dtsi"
17 compatible = "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp";
26 #address-cells = <1>;
27 #size-cells = <0>;
28 enable-method = "marvell,armada-xp-smp";
32 compatible = "marvell,sheeva-v7";
35 clock-latency = <1000000>;
40 compatible = "marvell,sheeva-v7";
[all …]
Darmada-385-db-ap.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
4 * (DB-88F6820-AP)
11 /dts-v1/;
12 #include "armada-385.dtsi"
14 #include <dt-bindings/gpio/gpio.h>
18 compatible = "marvell,a385-db-ap", "marvell,armada385", "marvell,armada380";
21 stdout-path = "serial1:115200n8";
36 internal-regs {
38 pinctrl-names = "default";
39 pinctrl-0 = <&i2c0_pins>;
[all …]
/Linux-v5.15/Documentation/devicetree/bindings/phy/
Dti,phy-j721e-wiz.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: "http://devicetree.org/schemas/phy/ti,phy-j721e-wiz.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
11 - Kishon Vijay Abraham I <kishon@ti.com>
16 - ti,j721e-wiz-16g
17 - ti,j721e-wiz-10g
18 - ti,am64-wiz-10g
20 power-domains:
[all …]
/Linux-v5.15/Documentation/devicetree/bindings/pci/
Dti-pci.txt4 - compatible: Should be "ti,dra7-pcie" for RC (deprecated)
5 Should be "ti,dra7-pcie-ep" for EP (deprecated)
6 Should be "ti,dra746-pcie-rc" for dra74x/dra76 in RC mode
7 Should be "ti,dra746-pcie-ep" for dra74x/dra76 in EP mode
8 Should be "ti,dra726-pcie-rc" for dra72x in RC mode
9 Should be "ti,dra726-pcie-ep" for dra72x in EP mode
10 - phys : list of PHY specifiers (used by generic PHY framework)
11 - phy-names : must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the
13 - ti,hwmods : Name of the hwmod associated to the pcie, "pcie<X>",
15 - num-lanes as specified in ../snps,dw-pcie.yaml
[all …]
/Linux-v5.15/drivers/phy/
Dphy-xgene.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * AppliedMicro X-Gene Multi-purpose PHY driver
10 * The APM X-Gene PHY consists of two PLL clock macro's (CMU) and lanes.
19 * -----------------
20 * | Internal | |------|
21 * | Ref PLL CMU |----| | ------------- ---------
22 * ------------ ---- | MUX |-----|PHY PLL CMU|----| Serdes|
23 * | | | | ---------
24 * External Clock ------| | -------------
25 * |------|
[all …]
/Linux-v5.15/drivers/nvdimm/
Dbtt.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright (c) 2014-2015, Intel Corporation.
19 #include <linux/backing-dev.h>
30 return &arena->nd_btt->dev; in to_dev()
35 return offset + nd_btt->initial_offset; in adjust_initial_offset()
41 struct nd_btt *nd_btt = arena->nd_btt; in arena_read_bytes()
42 struct nd_namespace_common *ndns = nd_btt->ndns; in arena_read_bytes()
52 struct nd_btt *nd_btt = arena->nd_btt; in arena_write_bytes()
53 struct nd_namespace_common *ndns = nd_btt->ndns; in arena_write_bytes()
69 dev_WARN_ONCE(to_dev(arena), !IS_ALIGNED(arena->infooff, 512), in btt_info_write()
[all …]
/Linux-v5.15/include/media/
Dv4l2-fwnode.h1 /* SPDX-License-Identifier: GPL-2.0-only */
8 * Copyright (C) 2012 - 2013 Samsung Electronics Co., Ltd.
22 #include <media/v4l2-mediabus.h>
31 * struct v4l2_fwnode_bus_mipi_csi2 - MIPI CSI-2 bus data structure
33 * @data_lanes: an array of physical data lane indexes
34 * @clock_lane: physical lane index of the clock lane
48 * struct v4l2_fwnode_bus_parallel - parallel data bus data structure
60 * struct v4l2_fwnode_bus_mipi_csi1 - CSI-1/CCP2 data bus structure
62 * false - not inverted, true - inverted
63 * @strobe: false - data/clock, true - data/strobe
[all …]
/Linux-v5.15/Documentation/devicetree/bindings/display/bridge/
Dps8640.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nicolas Boichat <drinkcat@chromium.org>
11 - Enric Balletbo i Serra <enric.balletbo@collabora.com>
14 The PS8640 is a low power MIPI-to-eDP video format converter supporting
17 plus clock, at a transmission rate up to 1.5Gbit/sec per lane. The
18 device outputs eDP v1.4, one or two lanes, at a link rate of up to
19 3.24Gbit/sec per lane.
29 powerdown-gpios:
[all …]
/Linux-v5.15/drivers/net/ethernet/sfc/falcon/
Dtxc43128_phy.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright 2006-2011 Solarflare Communications Inc.
9 * see www.transwitch.com, part is TXC-43128
30 * Compile-time config
52 /* Lane power-down */
56 * initiates a logic reset. Self-clearing */
63 /* Lane selection */
69 /* Lane power-down */
79 /* Bit position of value for lane 0 (or 2) */
81 /* Bit position of value for lane 1 (or 3) */
[all …]
/Linux-v5.15/net/atm/
Dlec.h1 /* SPDX-License-Identifier: GPL-2.0 */
36 * Operations that LANE2 capable device can do. Two first functions
40 * top of the LANE device. The MPOA component assigns it's own function
41 * to (*associate_indicator)() and the LANE device will use that
144 struct lane2_ops *lane2_ops; /* can be NULL for LANE v1 */
153 #define LEC_VCC_PRIV(vcc) ((struct lec_vcc_priv *)((vcc)->user_back))

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