| /Linux-v6.1/Documentation/devicetree/bindings/clock/ |
| D | mediatek,topckgen.yaml | 4 $id: "http://devicetree.org/schemas/clock/mediatek,topckgen.yaml#"
14 The Mediatek topckgen controller provides various clocks to the system.
21 - mediatek,mt6797-topckgen
22 - mediatek,mt7622-topckgen
23 - mediatek,mt8135-topckgen
24 - mediatek,mt8173-topckgen
25 - mediatek,mt8516-topckgen
27 - const: mediatek,mt7623-topckgen
28 - const: mediatek,mt2701-topckgen
32 - mediatek,mt2701-topckgen
[all …]
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| D | mediatek,mt8365-sys-clock.yaml | 14 The topckgen provides dividers and muxes which provides the clock source to other IP blocks.
21 - mediatek,mt8365-topckgen
43 topckgen: clock-controller@10000000 {
44 compatible = "mediatek,mt8365-topckgen", "syscon";
|
| /Linux-v6.1/Documentation/devicetree/bindings/sound/ |
| D | mt8186-afe-pcm.yaml | 36 mediatek,topckgen:
38 description: The phandle of the mediatek topckgen controller
103 - mediatek,topckgen
122 mediatek,topckgen = <&topckgen>;
125 <&topckgen 15>, //CLK_TOP_AUDIO
126 <&topckgen 16>, //CLK_TOP_AUD_INTBUS
127 <&topckgen 70>, //CLK_TOP_MAINPLL_D2_D4
128 <&topckgen 17>, //CLK_TOP_AUD_1
130 <&topckgen 18>, //CLK_TOP_AUD_2
132 <&topckgen 19>, //CLK_TOP_AUD_ENGEN1
[all …]
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| D | mt2701-afe-pcm.txt | 69 <&topckgen CLK_TOP_AUD_MUX1_SEL>,
70 <&topckgen CLK_TOP_AUD_MUX2_SEL>,
71 <&topckgen CLK_TOP_AUD_48K_TIMING>,
72 <&topckgen CLK_TOP_AUD_44K_TIMING>,
73 <&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
74 <&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
75 <&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
76 <&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
77 <&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
78 <&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
[all …]
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| D | mt8195-afe-pcm.yaml | 34 mediatek,topckgen:
36 description: The phandle of the mediatek topckgen controller
138 - mediatek,topckgen
157 mediatek,topckgen = <&topckgen>;
161 <&topckgen 163>, //CLK_TOP_APLL1
162 <&topckgen 166>, //CLK_TOP_APLL2
163 <&topckgen 233>, //CLK_TOP_APLL12_DIV0
164 <&topckgen 234>, //CLK_TOP_APLL12_DIV1
165 <&topckgen 235>, //CLK_TOP_APLL12_DIV2
166 <&topckgen 236>, //CLK_TOP_APLL12_DIV3
[all …]
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| D | mtk-afe-pcm.txt | 26 <&topckgen TOP_AUDIO_SEL>,
27 <&topckgen TOP_AUD_INTBUS_SEL>,
28 <&topckgen TOP_APLL1_DIV0>,
29 <&topckgen TOP_APLL2_DIV0>,
30 <&topckgen TOP_I2S0_M_CK_SEL>,
31 <&topckgen TOP_I2S1_M_CK_SEL>,
32 <&topckgen TOP_I2S2_M_CK_SEL>,
33 <&topckgen TOP_I2S3_M_CK_SEL>,
34 <&topckgen TOP_I2S3_B_CK_SEL>;
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| D | mt6797-afe-pcm.txt | 29 <&topckgen CLK_TOP_MUX_AUDIO>,
30 <&topckgen CLK_TOP_MUX_AUD_INTBUS>,
31 <&topckgen CLK_TOP_SYSPLL3_D4>,
32 <&topckgen CLK_TOP_SYSPLL1_D4>,
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| D | mt8192-afe-pcm.yaml | 34 mediatek,topckgen:
36 description: The phandle of the mediatek topckgen controller
64 - mediatek,topckgen
86 mediatek,topckgen = <&topckgen>;
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| /Linux-v6.1/arch/arm64/boot/dts/mediatek/ |
| D | mt8516.dtsi | 58 <&topckgen CLK_TOP_MAINPLL_D2>;
71 <&topckgen CLK_TOP_MAINPLL_D2>;
84 <&topckgen CLK_TOP_MAINPLL_D2>;
97 <&topckgen CLK_TOP_MAINPLL_D2>;
182 topckgen: topckgen@10000000 { label
183 compatible = "mediatek,mt8516-topckgen", "syscon";
218 clocks = <&topckgen CLK_TOP_CLK26M_D2>,
219 <&topckgen CLK_TOP_APXGPT>;
252 clocks = <&topckgen CLK_TOP_PMICWRAP_26M>,
253 <&topckgen CLK_TOP_PMICWRAP_AP>;
[all …]
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| D | mt8192.dtsi | 274 topckgen: syscon@10000000 { label
275 compatible = "mediatek,mt8192-topckgen", "syscon";
332 clocks = <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
350 clocks = <&topckgen CLK_TOP_MFG_PLL_SEL>;
392 clocks = <&topckgen CLK_TOP_DISP_SEL>,
406 clocks = <&topckgen CLK_TOP_IPE_SEL>,
419 clocks = <&topckgen CLK_TOP_IMG1_SEL>,
429 clocks = <&topckgen CLK_TOP_IMG2_SEL>,
439 clocks = <&topckgen CLK_TOP_MDP_SEL>,
448 clocks = <&topckgen CLK_TOP_VENC_SEL>,
[all …]
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| D | mt8195.dtsi | 320 topckgen: syscon@10000000 { label
321 compatible = "mediatek,mt8195-topckgen", "syscon";
416 clocks = <&topckgen CLK_TOP_VPP>,
417 <&topckgen CLK_TOP_CAM>,
418 <&topckgen CLK_TOP_CCU>,
419 <&topckgen CLK_TOP_IMG>,
420 <&topckgen CLK_TOP_VENC>,
421 <&topckgen CLK_TOP_VDEC>,
422 <&topckgen CLK_TOP_WPE_VPP>,
423 <&topckgen CLK_TOP_CFG_VPP0>,
[all …]
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| D | mt7622.dtsi | 250 clocks = <&topckgen CLK_TOP_HIF_SEL>;
259 <&topckgen CLK_TOP_AXI_SEL>;
292 topckgen: topckgen@10210000 { label
293 compatible = "mediatek,mt7622-topckgen",
332 clocks = <&topckgen CLK_TOP_RTC>;
396 clocks = <&topckgen CLK_TOP_UART_SEL>,
407 clocks = <&topckgen CLK_TOP_UART_SEL>,
418 clocks = <&topckgen CLK_TOP_UART_SEL>,
429 clocks = <&topckgen CLK_TOP_UART_SEL>,
439 clocks = <&topckgen CLK_TOP_PWM_SEL>,
[all …]
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| D | mt8173.dtsi | 349 topckgen: clock-controller@10000000 { label
350 compatible = "mediatek,mt8173-topckgen";
460 clocks = <&topckgen CLK_TOP_MM_SEL>;
466 clocks = <&topckgen CLK_TOP_MM_SEL>,
467 <&topckgen CLK_TOP_VENC_SEL>;
473 clocks = <&topckgen CLK_TOP_MM_SEL>;
479 clocks = <&topckgen CLK_TOP_MM_SEL>;
486 clocks = <&topckgen CLK_TOP_MM_SEL>,
487 <&topckgen CLK_TOP_VENC_LT_SEL>;
535 <&topckgen CLK_TOP_RTC_SEL>;
[all …]
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| D | mt2712e.dtsi | 90 <&topckgen CLK_TOP_F_MP0_PLL1>;
103 <&topckgen CLK_TOP_F_MP0_PLL1>;
116 <&topckgen CLK_TOP_F_BIG_PLL1>;
246 topckgen: syscon@10000000 { label
247 compatible = "mediatek,mt2712-topckgen", "syscon";
285 clocks = <&topckgen CLK_TOP_MM_SEL>,
286 <&topckgen CLK_TOP_MFG_SEL>,
287 <&topckgen CLK_TOP_VENC_SEL>,
288 <&topckgen CLK_TOP_JPGDEC_SEL>,
289 <&topckgen CLK_TOP_A1SYS_HP_SEL>,
[all …]
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| D | mt7986a.dtsi | 115 topckgen: topckgen@1001b000 { label
116 compatible = "mediatek,mt7986-topckgen", "syscon";
188 assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
190 assigned-clock-parents = <&topckgen CLK_TOP_XTAL>,
191 <&topckgen CLK_TOP_UART_SEL>;
204 assigned-clock-parents = <&topckgen CLK_TOP_F26M_SEL>;
217 assigned-clock-parents = <&topckgen CLK_TOP_F26M_SEL>;
273 <&topckgen CLK_TOP_NETSYS_SEL>,
274 <&topckgen CLK_TOP_NETSYS_500M_SEL>;
281 assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>,
[all …]
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| D | mt8167.dtsi | 20 topckgen: topckgen@10000000 { label
21 compatible = "mediatek,mt8167-topckgen", "syscon";
51 clocks = <&topckgen CLK_TOP_SMI_MM>;
59 clocks = <&topckgen CLK_TOP_SMI_MM>,
60 <&topckgen CLK_TOP_RG_VDEC>;
67 clocks = <&topckgen CLK_TOP_SMI_MM>;
74 clocks = <&topckgen CLK_TOP_RG_AXI_MFG>,
75 <&topckgen CLK_TOP_RG_SLOW_MFG>;
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| D | mt8183.dtsi | 286 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
335 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
351 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
367 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
383 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
399 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
415 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
431 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
447 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
720 topckgen: syscon@10000000 { label
[all …]
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| D | mt8186.dtsi | 294 topckgen: syscon@10000000 { label
295 compatible = "mediatek,mt8186-topckgen", "syscon";
375 clocks = <&topckgen CLK_TOP_SPINOR>,
380 assigned-clocks = <&topckgen CLK_TOP_SPINOR>;
381 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D3_D8>;
546 clocks = <&topckgen CLK_TOP_MAINPLL_D5>,
547 <&topckgen CLK_TOP_SPI>,
558 clocks = <&topckgen CLK_TOP_DISP_PWM>,
570 clocks = <&topckgen CLK_TOP_MAINPLL_D5>,
571 <&topckgen CLK_TOP_SPI>,
[all …]
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| /Linux-v6.1/arch/arm/boot/dts/ |
| D | mt7629.dtsi | 98 clocks = <&topckgen CLK_TOP_HIF_SEL>;
100 assigned-clocks = <&topckgen CLK_TOP_HIF_SEL>;
101 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>;
138 topckgen: syscon@10210000 { label
139 compatible = "mediatek,mt7629-topckgen", "syscon";
216 clocks = <&topckgen CLK_TOP_UART_SEL>,
227 clocks = <&topckgen CLK_TOP_UART_SEL>,
238 clocks = <&topckgen CLK_TOP_UART_SEL>,
248 clocks = <&topckgen CLK_TOP_PWM_SEL>,
252 assigned-clocks = <&topckgen CLK_TOP_PWM_SEL>;
[all …]
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| D | mt2701.dtsi | 126 topckgen: syscon@10000000 { label
127 compatible = "mediatek,mt2701-topckgen", "syscon";
156 clocks = <&topckgen CLK_TOP_MM_SEL>,
157 <&topckgen CLK_TOP_MFG_SEL>,
158 <&topckgen CLK_TOP_ETHIF_SEL>;
343 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
344 <&topckgen CLK_TOP_SPI0_SEL>,
390 <&topckgen CLK_TOP_FLASH_SEL>;
403 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
404 <&topckgen CLK_TOP_SPI1_SEL>,
[all …]
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| D | mt7623.dtsi | 226 topckgen: syscon@10000000 { label
227 compatible = "mediatek,mt7623-topckgen",
228 "mediatek,mt2701-topckgen",
278 clocks = <&topckgen CLK_TOP_MM_SEL>,
279 <&topckgen CLK_TOP_MFG_SEL>,
280 <&topckgen CLK_TOP_ETHIF_SEL>;
424 clocks = <&topckgen CLK_TOP_PWM_SEL>,
488 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
489 <&topckgen CLK_TOP_SPI0_SEL>,
553 <&topckgen CLK_TOP_FLASH_SEL>;
[all …]
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| /Linux-v6.1/Documentation/devicetree/bindings/media/ |
| D | mediatek,vcodec-decoder.yaml | 143 <&topckgen CLK_TOP_UNIVPLL_D2>,
144 <&topckgen CLK_TOP_CCI400_SEL>,
145 <&topckgen CLK_TOP_VDEC_SEL>,
146 <&topckgen CLK_TOP_VCODECPLL>,
148 <&topckgen CLK_TOP_VENC_LT_SEL>,
149 <&topckgen CLK_TOP_VCODECPLL_370P5>;
158 assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>,
159 <&topckgen CLK_TOP_CCI400_SEL>,
160 <&topckgen CLK_TOP_VDEC_SEL>,
163 assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>,
[all …]
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| D | mediatek,vcodec-encoder.yaml | 156 clocks = <&topckgen CLK_TOP_VENC_SEL>;
158 assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>;
159 assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL>;
176 clocks = <&topckgen CLK_TOP_VENC_LT_SEL>;
178 assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>;
179 assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>;
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| /Linux-v6.1/Documentation/devicetree/bindings/net/ |
| D | mediatek-dwmac.yaml | 168 <&topckgen CLK_TOP_ETHER_125M_SEL>,
169 <&topckgen CLK_TOP_ETHER_50M_SEL>,
170 <&topckgen CLK_TOP_ETHER_50M_RMII_SEL>;
171 assigned-clocks = <&topckgen CLK_TOP_ETHER_125M_SEL>,
172 <&topckgen CLK_TOP_ETHER_50M_SEL>,
173 <&topckgen CLK_TOP_ETHER_50M_RMII_SEL>;
174 assigned-clock-parents = <&topckgen CLK_TOP_ETHERPLL_125M>,
175 <&topckgen CLK_TOP_APLL1_D3>,
176 <&topckgen CLK_TOP_ETHERPLL_50M>;
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| /Linux-v6.1/Documentation/devicetree/bindings/arm/mediatek/ |
| D | mediatek,mt8186-sys-clock.yaml | 21 The topckgen provides dividers and muxes which provide the clock source to other IP blocks.
31 - mediatek,mt8186-topckgen
53 topckgen: syscon@10000000 {
54 compatible = "mediatek,mt8186-topckgen", "syscon";
|
