| /Linux-v5.15/Documentation/devicetree/bindings/arm/mediatek/ |
| D | mediatek,topckgen.txt | 1 Mediatek topckgen controller
4 The Mediatek topckgen controller provides various clocks to the system.
9 - "mediatek,mt2701-topckgen"
10 - "mediatek,mt2712-topckgen", "syscon"
11 - "mediatek,mt6765-topckgen", "syscon"
12 - "mediatek,mt6779-topckgen", "syscon"
13 - "mediatek,mt6797-topckgen"
14 - "mediatek,mt7622-topckgen"
15 - "mediatek,mt7623-topckgen", "mediatek,mt2701-topckgen"
16 - "mediatek,mt7629-topckgen"
[all …]
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| D | mediatek,mt8192-sys-clock.yaml | 20 - mediatek,mt8192-topckgen
40 topckgen: syscon@10000000 {
41 compatible = "mediatek,mt8192-topckgen", "syscon";
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| /Linux-v5.15/Documentation/devicetree/bindings/sound/ |
| D | mt2701-afe-pcm.txt | 69 <&topckgen CLK_TOP_AUD_MUX1_SEL>,
70 <&topckgen CLK_TOP_AUD_MUX2_SEL>,
71 <&topckgen CLK_TOP_AUD_48K_TIMING>,
72 <&topckgen CLK_TOP_AUD_44K_TIMING>,
73 <&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
74 <&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
75 <&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
76 <&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
77 <&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
78 <&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
[all …]
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| D | mt8195-afe-pcm.yaml | 22 mediatek,topckgen:
24 description: The phandle of the mediatek topckgen controller
124 - mediatek,topckgen
140 mediatek,topckgen = <&topckgen>;
143 <&topckgen 163>, //CLK_TOP_APLL1
144 <&topckgen 166>, //CLK_TOP_APLL2
145 <&topckgen 233>, //CLK_TOP_APLL12_DIV0
146 <&topckgen 234>, //CLK_TOP_APLL12_DIV1
147 <&topckgen 235>, //CLK_TOP_APLL12_DIV2
148 <&topckgen 236>, //CLK_TOP_APLL12_DIV3
[all …]
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| D | mtk-afe-pcm.txt | 26 <&topckgen TOP_AUDIO_SEL>,
27 <&topckgen TOP_AUD_INTBUS_SEL>,
28 <&topckgen TOP_APLL1_DIV0>,
29 <&topckgen TOP_APLL2_DIV0>,
30 <&topckgen TOP_I2S0_M_CK_SEL>,
31 <&topckgen TOP_I2S1_M_CK_SEL>,
32 <&topckgen TOP_I2S2_M_CK_SEL>,
33 <&topckgen TOP_I2S3_M_CK_SEL>,
34 <&topckgen TOP_I2S3_B_CK_SEL>;
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| D | mt6797-afe-pcm.txt | 29 <&topckgen CLK_TOP_MUX_AUDIO>,
30 <&topckgen CLK_TOP_MUX_AUD_INTBUS>,
31 <&topckgen CLK_TOP_SYSPLL3_D4>,
32 <&topckgen CLK_TOP_SYSPLL1_D4>,
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| D | mt8183-afe-pcm.txt | 32 <&topckgen CLK_TOP_MUX_AUDIO>,
33 <&topckgen CLK_TOP_MUX_AUD_INTBUS>,
34 <&topckgen CLK_TOP_SYSPLL_D2_D4>,
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| /Linux-v5.15/arch/arm64/boot/dts/mediatek/ |
| D | mt8516.dtsi | 58 <&topckgen CLK_TOP_MAINPLL_D2>;
71 <&topckgen CLK_TOP_MAINPLL_D2>;
84 <&topckgen CLK_TOP_MAINPLL_D2>;
97 <&topckgen CLK_TOP_MAINPLL_D2>;
182 topckgen: topckgen@10000000 { label
183 compatible = "mediatek,mt8516-topckgen", "syscon";
218 clocks = <&topckgen CLK_TOP_CLK26M_D2>,
219 <&topckgen CLK_TOP_APXGPT>;
252 clocks = <&topckgen CLK_TOP_PMICWRAP_26M>,
253 <&topckgen CLK_TOP_PMICWRAP_AP>;
[all …]
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| D | mt7622.dtsi | 243 clocks = <&topckgen CLK_TOP_HIF_SEL>;
252 <&topckgen CLK_TOP_AXI_SEL>;
285 topckgen: topckgen@10210000 { label
286 compatible = "mediatek,mt7622-topckgen",
325 clocks = <&topckgen CLK_TOP_RTC>;
389 clocks = <&topckgen CLK_TOP_UART_SEL>,
400 clocks = <&topckgen CLK_TOP_UART_SEL>,
411 clocks = <&topckgen CLK_TOP_UART_SEL>,
422 clocks = <&topckgen CLK_TOP_UART_SEL>,
432 clocks = <&topckgen CLK_TOP_PWM_SEL>,
[all …]
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| D | mt8173.dtsi | 356 topckgen: clock-controller@10000000 { label
357 compatible = "mediatek,mt8173-topckgen";
468 clocks = <&topckgen CLK_TOP_MM_SEL>;
474 clocks = <&topckgen CLK_TOP_MM_SEL>,
475 <&topckgen CLK_TOP_VENC_SEL>;
481 clocks = <&topckgen CLK_TOP_MM_SEL>;
487 clocks = <&topckgen CLK_TOP_MM_SEL>;
494 clocks = <&topckgen CLK_TOP_MM_SEL>,
495 <&topckgen CLK_TOP_VENC_LT_SEL>;
543 <&topckgen CLK_TOP_RTC_SEL>;
[all …]
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| D | mt2712e.dtsi | 90 <&topckgen CLK_TOP_F_MP0_PLL1>;
103 <&topckgen CLK_TOP_F_MP0_PLL1>;
116 <&topckgen CLK_TOP_F_BIG_PLL1>;
246 topckgen: syscon@10000000 { label
247 compatible = "mediatek,mt2712-topckgen", "syscon";
285 clocks = <&topckgen CLK_TOP_MM_SEL>,
286 <&topckgen CLK_TOP_MFG_SEL>,
287 <&topckgen CLK_TOP_VENC_SEL>,
288 <&topckgen CLK_TOP_JPGDEC_SEL>,
289 <&topckgen CLK_TOP_A1SYS_HP_SEL>,
[all …]
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| D | mt8167.dtsi | 20 topckgen: topckgen@10000000 { label
21 compatible = "mediatek,mt8167-topckgen", "syscon";
52 clocks = <&topckgen CLK_TOP_SMI_MM>;
60 clocks = <&topckgen CLK_TOP_SMI_MM>,
61 <&topckgen CLK_TOP_RG_VDEC>;
68 clocks = <&topckgen CLK_TOP_SMI_MM>;
75 clocks = <&topckgen CLK_TOP_RG_AXI_MFG>,
76 <&topckgen CLK_TOP_RG_SLOW_MFG>;
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| D | mt8183.dtsi | 370 topckgen: syscon@10000000 { label
371 compatible = "mediatek,mt8183-topckgen", "syscon";
428 clocks = <&topckgen CLK_TOP_MUX_AUD_INTBUS>,
443 clocks = <&topckgen CLK_TOP_MUX_MFG>;
475 clocks = <&topckgen CLK_TOP_MUX_MM>,
497 clocks = <&topckgen CLK_TOP_MUX_CAM>,
515 clocks = <&topckgen CLK_TOP_MUX_IMG>,
538 clocks = <&topckgen CLK_TOP_MUX_IPU_IF>,
539 <&topckgen CLK_TOP_MUX_DSP>,
556 clocks = <&topckgen CLK_TOP_MUX_DSP1>;
[all …]
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| D | mt6797.dtsi | 114 topckgen: topckgen@10000000 { label
115 compatible = "mediatek,mt6797-topckgen";
213 clocks = <&topckgen CLK_TOP_MUX_MFG>,
214 <&topckgen CLK_TOP_MUX_MM>,
215 <&topckgen CLK_TOP_MUX_VDEC>;
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| /Linux-v5.15/Documentation/devicetree/bindings/media/ |
| D | mediatek-vcodec.txt | 61 <&topckgen CLK_TOP_UNIVPLL_D2>,
62 <&topckgen CLK_TOP_CCI400_SEL>,
63 <&topckgen CLK_TOP_VDEC_SEL>,
64 <&topckgen CLK_TOP_VCODECPLL>,
66 <&topckgen CLK_TOP_VENC_LT_SEL>,
67 <&topckgen CLK_TOP_VCODECPLL_370P5>;
76 assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>,
77 <&topckgen CLK_TOP_CCI400_SEL>,
78 <&topckgen CLK_TOP_VDEC_SEL>,
81 assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>,
[all …]
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| /Linux-v5.15/arch/arm/boot/dts/ |
| D | mt7629.dtsi | 98 clocks = <&topckgen CLK_TOP_HIF_SEL>;
100 assigned-clocks = <&topckgen CLK_TOP_HIF_SEL>;
101 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>;
138 topckgen: syscon@10210000 { label
139 compatible = "mediatek,mt7629-topckgen", "syscon";
216 clocks = <&topckgen CLK_TOP_UART_SEL>,
227 clocks = <&topckgen CLK_TOP_UART_SEL>,
238 clocks = <&topckgen CLK_TOP_UART_SEL>,
248 clocks = <&topckgen CLK_TOP_PWM_SEL>,
252 assigned-clocks = <&topckgen CLK_TOP_PWM_SEL>;
[all …]
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| D | mt2701.dtsi | 126 topckgen: syscon@10000000 { label
127 compatible = "mediatek,mt2701-topckgen", "syscon";
156 clocks = <&topckgen CLK_TOP_MM_SEL>,
157 <&topckgen CLK_TOP_MFG_SEL>,
158 <&topckgen CLK_TOP_ETHIF_SEL>;
343 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
344 <&topckgen CLK_TOP_SPI0_SEL>,
390 <&topckgen CLK_TOP_FLASH_SEL>;
403 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
404 <&topckgen CLK_TOP_SPI1_SEL>,
[all …]
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| D | mt7623.dtsi | 226 topckgen: syscon@10000000 { label
227 compatible = "mediatek,mt7623-topckgen",
228 "mediatek,mt2701-topckgen",
278 clocks = <&topckgen CLK_TOP_MM_SEL>,
279 <&topckgen CLK_TOP_MFG_SEL>,
280 <&topckgen CLK_TOP_ETHIF_SEL>;
424 clocks = <&topckgen CLK_TOP_PWM_SEL>,
488 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
489 <&topckgen CLK_TOP_SPI0_SEL>,
553 <&topckgen CLK_TOP_FLASH_SEL>;
[all …]
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| /Linux-v5.15/Documentation/devicetree/bindings/spi/ |
| D | spi-slave-mt27xx.txt | 14 - assigned-clocks: it's mux clock, should be <&topckgen CLK_TOP_SPISLV_SEL>.
17 - <&topckgen CLK_TOP_UNIVPLL1_D2>: specify parent clock 312MHZ.
19 - <&topckgen CLK_TOP_UNIVPLL1_D4>: specify parent clock 156MHZ.
20 - <&topckgen CLK_TOP_UNIVPLL2_D4>: specify parent clock 104MHZ.
21 - <&topckgen CLK_TOP_UNIVPLL1_D8>: specify parent clock 78MHZ.
31 assigned-clocks = <&topckgen CLK_TOP_SPISLV_SEL>;
32 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>;
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| D | spi-mt65xx.txt | 31 - <&topckgen CLK_TOP_SYSPLL3_D2>: specify parent clock 109MHZ.
33 - <&topckgen CLK_TOP_SYSPLL4_D2>: specify parent clock 78MHZ.
34 - <&topckgen CLK_TOP_UNIVPLL2_D4>: specify parent clock 104MHZ.
35 - <&topckgen CLK_TOP_UNIVPLL1_D8>: specify parent clock 78MHZ.
36 The second should be <&topckgen CLK_TOP_SPI_SEL>. It's clock mux.
62 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
63 <&topckgen CLK_TOP_SPI_SEL>,
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| /Linux-v5.15/Documentation/devicetree/bindings/net/ |
| D | mediatek-dwmac.txt | 71 <&topckgen CLK_TOP_ETHER_125M_SEL>,
72 <&topckgen CLK_TOP_ETHER_50M_SEL>,
73 <&topckgen CLK_TOP_ETHER_50M_RMII_SEL>;
74 assigned-clocks = <&topckgen CLK_TOP_ETHER_125M_SEL>,
75 <&topckgen CLK_TOP_ETHER_50M_SEL>,
76 <&topckgen CLK_TOP_ETHER_50M_RMII_SEL>;
77 assigned-clock-parents = <&topckgen CLK_TOP_ETHERPLL_125M>,
78 <&topckgen CLK_TOP_APLL1_D3>,
79 <&topckgen CLK_TOP_ETHERPLL_50M>;
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| D | mediatek,star-emac.yaml | 76 clocks = <&topckgen CLK_TOP_RG_ETH>,
77 <&topckgen CLK_TOP_66M_ETH>,
78 <&topckgen CLK_TOP_133M_ETH>;
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| /Linux-v5.15/Documentation/devicetree/bindings/power/ |
| D | mediatek,power-controller.yaml | 242 clocks = <&topckgen CLK_TOP_MM_SEL>;
248 clocks = <&topckgen CLK_TOP_MM_SEL>,
249 <&topckgen CLK_TOP_VENC_SEL>;
255 clocks = <&topckgen CLK_TOP_MM_SEL>;
261 clocks = <&topckgen CLK_TOP_MM_SEL>;
268 clocks = <&topckgen CLK_TOP_MM_SEL>,
269 <&topckgen CLK_TOP_VENC_LT_SEL>;
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| /Linux-v5.15/Documentation/devicetree/bindings/soc/mediatek/ |
| D | scpsys.txt | 67 <&topckgen CLK_TOP_MM_SEL>;
68 <&topckgen CLK_TOP_VENC_SEL>,
69 <&topckgen CLK_TOP_VENC_LT_SEL>;
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| /Linux-v5.15/Documentation/devicetree/bindings/mmc/ |
| D | mtk-sd.yaml | 164 <&topckgen CLK_TOP_MSDC50_0_H_SEL>;
169 assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>;
170 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
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