| /Linux-v5.4/drivers/gpu/drm/tegra/ |
| D | mipi-phy.c | 16 int mipi_dphy_timing_get_default(struct mipi_dphy_timing *timing, in mipi_dphy_timing_get_default() argument
19 timing->clkmiss = 0; in mipi_dphy_timing_get_default()
20 timing->clkpost = 70 + 52 * period; in mipi_dphy_timing_get_default()
21 timing->clkpre = 8; in mipi_dphy_timing_get_default()
22 timing->clkprepare = 65; in mipi_dphy_timing_get_default()
23 timing->clksettle = 95; in mipi_dphy_timing_get_default()
24 timing->clktermen = 0; in mipi_dphy_timing_get_default()
25 timing->clktrail = 80; in mipi_dphy_timing_get_default()
26 timing->clkzero = 260; in mipi_dphy_timing_get_default()
27 timing->dtermen = 0; in mipi_dphy_timing_get_default()
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| /Linux-v5.4/drivers/gpu/drm/msm/dsi/phy/ |
| D | dsi_phy.c | 26 static void dsi_dphy_timing_calc_clk_zero(struct msm_dsi_dphy_timing *timing, in dsi_dphy_timing_calc_clk_zero() argument
33 temp = 300 * coeff - ((timing->clk_prepare >> 1) + 1) * 2 * ui; in dsi_dphy_timing_calc_clk_zero()
44 temp = (timing->hs_rqst + timing->clk_prepare + clk_z) & 0x7; in dsi_dphy_timing_calc_clk_zero()
45 timing->clk_zero = clk_z + 8 - temp; in dsi_dphy_timing_calc_clk_zero()
48 int msm_dsi_dphy_timing_calc(struct msm_dsi_dphy_timing *timing, in msm_dsi_dphy_timing_calc() argument
70 timing->clk_prepare = linear_inter(tmax, tmin, pcnt0, 0, true); in msm_dsi_dphy_timing_calc()
74 timing->hs_rqst = temp; in msm_dsi_dphy_timing_calc()
76 timing->hs_rqst = max_t(s32, 0, temp - 2); in msm_dsi_dphy_timing_calc()
79 dsi_dphy_timing_calc_clk_zero(timing, ui, coeff, pcnt2); in msm_dsi_dphy_timing_calc()
84 timing->clk_trail = linear_inter(tmax, tmin, pcnt3, 0, true); in msm_dsi_dphy_timing_calc()
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| D | dsi_phy_14nm.c | 14 struct msm_dsi_dphy_timing *timing, in dsi_14nm_dphy_set_timing() argument
19 u32 zero = clk_ln ? timing->clk_zero : timing->hs_zero; in dsi_14nm_dphy_set_timing()
20 u32 prepare = clk_ln ? timing->clk_prepare : timing->hs_prepare; in dsi_14nm_dphy_set_timing()
21 u32 trail = clk_ln ? timing->clk_trail : timing->hs_trail; in dsi_14nm_dphy_set_timing()
22 u32 rqst = clk_ln ? timing->hs_rqst_ckln : timing->hs_rqst; in dsi_14nm_dphy_set_timing()
23 u32 prep_dly = clk_ln ? timing->hs_prep_dly_ckln : timing->hs_prep_dly; in dsi_14nm_dphy_set_timing()
24 u32 halfbyte_en = clk_ln ? timing->hs_halfbyte_en_ckln : in dsi_14nm_dphy_set_timing()
25 timing->hs_halfbyte_en; in dsi_14nm_dphy_set_timing()
28 DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT(timing->hs_exit)); in dsi_14nm_dphy_set_timing()
42 DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO(timing->ta_go) | in dsi_14nm_dphy_set_timing()
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| D | dsi_phy_20nm.c | 10 struct msm_dsi_dphy_timing *timing) in dsi_20nm_dphy_set_timing() argument
15 DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO(timing->clk_zero)); in dsi_20nm_dphy_set_timing()
17 DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL(timing->clk_trail)); in dsi_20nm_dphy_set_timing()
19 DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE(timing->clk_prepare)); in dsi_20nm_dphy_set_timing()
20 if (timing->clk_zero & BIT(8)) in dsi_20nm_dphy_set_timing()
24 DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT(timing->hs_exit)); in dsi_20nm_dphy_set_timing()
26 DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO(timing->hs_zero)); in dsi_20nm_dphy_set_timing()
28 DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE(timing->hs_prepare)); in dsi_20nm_dphy_set_timing()
30 DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL(timing->hs_trail)); in dsi_20nm_dphy_set_timing()
32 DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST(timing->hs_rqst)); in dsi_20nm_dphy_set_timing()
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| D | dsi_phy_28nm.c | 10 struct msm_dsi_dphy_timing *timing) in dsi_28nm_dphy_set_timing() argument
15 DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO(timing->clk_zero)); in dsi_28nm_dphy_set_timing()
17 DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL(timing->clk_trail)); in dsi_28nm_dphy_set_timing()
19 DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE(timing->clk_prepare)); in dsi_28nm_dphy_set_timing()
20 if (timing->clk_zero & BIT(8)) in dsi_28nm_dphy_set_timing()
24 DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT(timing->hs_exit)); in dsi_28nm_dphy_set_timing()
26 DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO(timing->hs_zero)); in dsi_28nm_dphy_set_timing()
28 DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE(timing->hs_prepare)); in dsi_28nm_dphy_set_timing()
30 DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL(timing->hs_trail)); in dsi_28nm_dphy_set_timing()
32 DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST(timing->hs_rqst)); in dsi_28nm_dphy_set_timing()
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| D | dsi_phy_28nm_8960.c | 12 struct msm_dsi_dphy_timing *timing) in dsi_28nm_dphy_set_timing() argument
17 DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO(timing->clk_zero)); in dsi_28nm_dphy_set_timing()
19 DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL(timing->clk_trail)); in dsi_28nm_dphy_set_timing()
21 DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE(timing->clk_prepare)); in dsi_28nm_dphy_set_timing()
24 DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT(timing->hs_exit)); in dsi_28nm_dphy_set_timing()
26 DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO(timing->hs_zero)); in dsi_28nm_dphy_set_timing()
28 DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE(timing->hs_prepare)); in dsi_28nm_dphy_set_timing()
30 DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL(timing->hs_trail)); in dsi_28nm_dphy_set_timing()
32 DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST(timing->hs_rqst)); in dsi_28nm_dphy_set_timing()
34 DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO(timing->ta_go) | in dsi_28nm_dphy_set_timing()
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| D | dsi_phy_10nm.c | 94 struct msm_dsi_dphy_timing *timing = &phy->timing; in dsi_10nm_phy_enable() local
100 if (msm_dsi_dphy_timing_calc_v3(timing, clk_req)) { in dsi_10nm_phy_enable()
102 "%s: D-PHY timing calculation failed\n", __func__); in dsi_10nm_phy_enable()
140 timing->hs_halfbyte_en); in dsi_10nm_phy_enable()
142 timing->clk_zero); in dsi_10nm_phy_enable()
144 timing->clk_prepare); in dsi_10nm_phy_enable()
146 timing->clk_trail); in dsi_10nm_phy_enable()
148 timing->hs_exit); in dsi_10nm_phy_enable()
150 timing->hs_zero); in dsi_10nm_phy_enable()
152 timing->hs_prepare); in dsi_10nm_phy_enable()
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| /Linux-v5.4/drivers/clk/tegra/ |
| D | clk-emc.c | 47 * When we change the timing to a timing with a parent that has the same
49 * timing that has a different clock source.
116 struct emc_timing *timing = NULL; in emc_determine_rate() local
132 timing = tegra->timings + i; in emc_determine_rate()
134 if (timing->rate < req->rate && i != t - 1) in emc_determine_rate()
137 if (timing->rate > req->max_rate) { in emc_determine_rate()
143 if (timing->rate < req->min_rate) in emc_determine_rate()
146 req->rate = timing->rate; in emc_determine_rate()
150 if (timing) { in emc_determine_rate()
151 req->rate = timing->rate; in emc_determine_rate()
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| /Linux-v5.4/drivers/memory/tegra/ |
| D | tegra124-emc.c | 478 /* Timing change sequence functions */
501 dev_err(emc->dev, "timing update timed out\n"); in emc_seq_update_timing()
539 struct emc_timing *timing = NULL; in tegra_emc_find_timing() local
544 timing = &emc->timings[i]; in tegra_emc_find_timing()
549 if (!timing) { in tegra_emc_find_timing()
550 dev_err(emc->dev, "no timing for rate %lu\n", rate); in tegra_emc_find_timing()
554 return timing; in tegra_emc_find_timing()
560 struct emc_timing *timing = tegra_emc_find_timing(emc, rate); in tegra_emc_prepare_timing_change() local
568 if (!timing) in tegra_emc_prepare_timing_change()
571 if ((last->emc_mode_1 & 0x1) == (timing->emc_mode_1 & 0x1)) in tegra_emc_prepare_timing_change()
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| D | tegra20-emc.c | 178 struct emc_timing *timing = NULL; in tegra_emc_find_timing() local
183 timing = &emc->timings[i]; in tegra_emc_find_timing()
188 if (!timing) { in tegra_emc_find_timing()
189 dev_err(emc->dev, "no timing for rate %lu\n", rate); in tegra_emc_find_timing()
193 return timing; in tegra_emc_find_timing()
198 struct emc_timing *timing = tegra_emc_find_timing(emc, rate); in emc_prepare_timing_change() local
201 if (!timing) in emc_prepare_timing_change()
204 dev_dbg(emc->dev, "%s: using timing rate %lu for requested rate %lu\n", in emc_prepare_timing_change()
205 __func__, timing->rate, rate); in emc_prepare_timing_change()
208 for (i = 0; i < ARRAY_SIZE(timing->data); i++) in emc_prepare_timing_change()
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| /Linux-v5.4/drivers/gpu/drm/nouveau/nvkm/subdev/bios/ |
| D | timing.c | 26 #include <subdev/bios/timing.h>
33 u32 timing = 0; in nvbios_timingTe() local
37 timing = nvbios_rd32(bios, bit_P.offset + 4); in nvbios_timingTe()
40 timing = nvbios_rd32(bios, bit_P.offset + 8); in nvbios_timingTe()
42 if (timing) { in nvbios_timingTe()
43 *ver = nvbios_rd08(bios, timing + 0); in nvbios_timingTe()
46 *hdr = nvbios_rd08(bios, timing + 1); in nvbios_timingTe()
47 *cnt = nvbios_rd08(bios, timing + 2); in nvbios_timingTe()
48 *len = nvbios_rd08(bios, timing + 3); in nvbios_timingTe()
51 return timing; in nvbios_timingTe()
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| /Linux-v5.4/drivers/devfreq/ |
| D | rk3399_dmc.c | 65 struct dram_timing timing; member
239 static int of_get_ddr_timings(struct dram_timing *timing, in of_get_ddr_timings() argument
245 &timing->ddr3_speed_bin); in of_get_ddr_timings()
247 &timing->pd_idle); in of_get_ddr_timings()
249 &timing->sr_idle); in of_get_ddr_timings()
251 &timing->sr_mc_gate_idle); in of_get_ddr_timings()
253 &timing->srpd_lite_idle); in of_get_ddr_timings()
255 &timing->standby_idle); in of_get_ddr_timings()
257 &timing->auto_pd_dis_freq); in of_get_ddr_timings()
259 &timing->dram_dll_dis_freq); in of_get_ddr_timings()
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| /Linux-v5.4/drivers/video/fbdev/ |
| D | gbefb.c | 37 struct gbe_timing_info timing; member
412 static void gbefb_setup_flatpanel(struct gbe_timing_info *timing) in gbefb_setup_flatpanel() argument
418 (timing->flags & FB_SYNC_HOR_HIGH_ACT) ? 0 : 1); in gbefb_setup_flatpanel()
420 (timing->flags & FB_SYNC_VERT_HIGH_ACT) ? 0 : 1); in gbefb_setup_flatpanel()
428 timing->pll_m = 4; in gbefb_setup_flatpanel()
429 timing->pll_n = 1; in gbefb_setup_flatpanel()
430 timing->pll_p = 0; in gbefb_setup_flatpanel()
457 struct gbe_timing_info *timing) in compute_gbe_timing() argument
468 /* Determine valid resolution and timing in compute_gbe_timing()
504 /* set video timing information */ in compute_gbe_timing()
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| /Linux-v5.4/drivers/video/fbdev/via/ |
| D | via_modesetting.c | 18 void via_set_primary_timing(const struct via_display_timing *timing) in via_set_primary_timing() argument
22 raw.hor_total = timing->hor_total / 8 - 5; in via_set_primary_timing()
23 raw.hor_addr = timing->hor_addr / 8 - 1; in via_set_primary_timing()
24 raw.hor_blank_start = timing->hor_blank_start / 8 - 1; in via_set_primary_timing()
25 raw.hor_blank_end = timing->hor_blank_end / 8 - 1; in via_set_primary_timing()
26 raw.hor_sync_start = timing->hor_sync_start / 8; in via_set_primary_timing()
27 raw.hor_sync_end = timing->hor_sync_end / 8; in via_set_primary_timing()
28 raw.ver_total = timing->ver_total - 2; in via_set_primary_timing()
29 raw.ver_addr = timing->ver_addr - 1; in via_set_primary_timing()
30 raw.ver_blank_start = timing->ver_blank_start - 1; in via_set_primary_timing()
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| /Linux-v5.4/drivers/gpu/drm/sti/ |
| D | sti_awg_utils.c | 122 struct awg_timing *timing) in awg_generate_line_signal() argument
127 if (timing->trailing_pixels > 0) { in awg_generate_line_signal()
129 val = timing->blanking_level; in awg_generate_line_signal()
132 val = timing->trailing_pixels - 1 + AWG_DELAY; in awg_generate_line_signal()
137 val = timing->blanking_level; in awg_generate_line_signal()
138 ret |= awg_generate_instr((timing->trailing_pixels > 0) ? SET : RPLSET, in awg_generate_line_signal()
141 if (timing->blanking_pixels > 0) { in awg_generate_line_signal()
143 val = timing->active_pixels - 1; in awg_generate_line_signal()
147 val = timing->blanking_level; in awg_generate_line_signal()
156 struct awg_timing *timing) in sti_awg_generate_code_data_enable_mode() argument
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| /Linux-v5.4/drivers/media/rc/img-ir/ |
| D | img-ir-hw.h | 22 /* Timing information */
53 * struct img_ir_timing_range - range of timing values
54 * @min: Minimum timing value
55 * @max: Maximum timing value (if < @min, this will be set to @min during
65 * struct img_ir_symbol_timing - timing data for a symbol
66 * @pulse: Timing range for the length of the pulse in this symbol
67 * @space: Timing range for the length of the space in this symbol
75 * struct img_ir_free_timing - timing data for free time symbol
88 * struct img_ir_timings - Timing values.
89 * @ldr: Leader symbol timing data
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| /Linux-v5.4/drivers/gpu/drm/amd/display/dc/dce110/ |
| D | dce110_timing_generator_v.c | 45 * DCE11 Timing Generator Implementation
244 const struct dc_crtc_timing *timing) in dce110_timing_generator_v_program_blanking() argument
246 uint32_t vsync_offset = timing->v_border_bottom + in dce110_timing_generator_v_program_blanking()
247 timing->v_front_porch; in dce110_timing_generator_v_program_blanking()
248 uint32_t v_sync_start = timing->v_addressable + vsync_offset; in dce110_timing_generator_v_program_blanking()
250 uint32_t hsync_offset = timing->h_border_right + in dce110_timing_generator_v_program_blanking()
251 timing->h_front_porch; in dce110_timing_generator_v_program_blanking()
252 uint32_t h_sync_start = timing->h_addressable + hsync_offset; in dce110_timing_generator_v_program_blanking()
263 timing->h_total - 1, in dce110_timing_generator_v_program_blanking()
272 timing->v_total - 1, in dce110_timing_generator_v_program_blanking()
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| /Linux-v5.4/drivers/gpu/drm/msm/disp/dpu1/ |
| D | dpu_encoder_phys_vid.c | 41 struct intf_timing_params *timing) in drm_mode_to_intf_timing_params() argument
43 memset(timing, 0, sizeof(*timing)); in drm_mode_to_intf_timing_params()
70 timing->width = mode->hdisplay; /* active width */ in drm_mode_to_intf_timing_params()
71 timing->height = mode->vdisplay; /* active height */ in drm_mode_to_intf_timing_params()
72 timing->xres = timing->width; in drm_mode_to_intf_timing_params()
73 timing->yres = timing->height; in drm_mode_to_intf_timing_params()
74 timing->h_back_porch = mode->htotal - mode->hsync_end; in drm_mode_to_intf_timing_params()
75 timing->h_front_porch = mode->hsync_start - mode->hdisplay; in drm_mode_to_intf_timing_params()
76 timing->v_back_porch = mode->vtotal - mode->vsync_end; in drm_mode_to_intf_timing_params()
77 timing->v_front_porch = mode->vsync_start - mode->vdisplay; in drm_mode_to_intf_timing_params()
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| /Linux-v5.4/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ |
| D | ramnv50.c | 34 #include <subdev/bios/timing.h>
73 nv50_ram_timing_calc(struct nv50_ram *ram, u32 *timing) in nv50_ram_timing_calc() argument
98 timing[6] = (0x2d + T(CL) - T(CWL) + in nv50_ram_timing_calc()
104 timing[6] = (0x2b + T(CL) - T(CWL)) << 16 | in nv50_ram_timing_calc()
109 timing[0] = (T(RP) << 24 | T(RAS) << 16 | T(RFC) << 8 | T(RC)); in nv50_ram_timing_calc()
110 timing[1] = (T(WR) + 1 + T(CWL)) << 24 | in nv50_ram_timing_calc()
114 timing[2] = (T(CWL) - 1) << 24 | in nv50_ram_timing_calc()
118 timing[3] = (unkt3b - 2 + T(CL)) << 24 | in nv50_ram_timing_calc()
122 timing[4] = (cur4 & 0xffff0000) | in nv50_ram_timing_calc()
125 timing[5] = T(RFC) << 24 | in nv50_ram_timing_calc()
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| /Linux-v5.4/drivers/ide/ |
| D | triflex.c | 29 u16 timing = 0; in triflex_set_mode() local
36 timing = 0x0103; in triflex_set_mode()
39 timing = 0x0203; in triflex_set_mode()
42 timing = 0x0808; in triflex_set_mode()
47 timing = 0x0f0f; in triflex_set_mode()
50 timing = 0x0202; in triflex_set_mode()
53 timing = 0x0204; in triflex_set_mode()
56 timing = 0x0404; in triflex_set_mode()
59 timing = 0x0508; in triflex_set_mode()
62 timing = 0x0808; in triflex_set_mode()
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| /Linux-v5.4/Documentation/driver-api/memory-devices/ |
| D | ti-gpmc.rst | 20 GPMC generic timing calculation:
29 generic timing routine was developed to achieve above requirements.
37 happen that timing as specified by peripheral datasheet is not present
38 in timing structure, in this scenario, try to correlate peripheral
39 timing to the one available. If that doesn't work, try to add a new
40 field as required by peripheral, educate generic timing routine to
45 Generic timing routine has been verified to work properly on
48 A word of caution: generic timing routine has been developed based
50 custom timing routines, a kind of reverse engineering without
52 in mainline having custom timing routine) and by simulation.
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| /Linux-v5.4/drivers/ata/ |
| D | pata_triflex.c | 62 * triflex_load_timing - timing configuration
76 u32 timing = 0; in triflex_load_timing() local
88 timing = 0x0103;break; in triflex_load_timing()
90 timing = 0x0203;break; in triflex_load_timing()
92 timing = 0x0808;break; in triflex_load_timing()
96 timing = 0x0F0F;break; in triflex_load_timing()
98 timing = 0x0202;break; in triflex_load_timing()
100 timing = 0x0204;break; in triflex_load_timing()
102 timing = 0x0404;break; in triflex_load_timing()
104 timing = 0x0508;break; in triflex_load_timing()
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| /Linux-v5.4/drivers/gpu/drm/amd/display/dc/dsc/ |
| D | dc_dsc.c | 282 /* Get DSC bandwidth range based on [min_bpp, max_bpp] target bitrate range, and timing's pixel clo…
289 const struct dc_crtc_timing *timing, in get_dsc_bandwidth_range() argument
293 range->stream_kbps = dc_bandwidth_in_kbps_from_timing(timing); in get_dsc_bandwidth_range()
296 range->max_kbps = dsc_div_by_10_round_up(max_bpp * timing->pix_clk_100hz); in get_dsc_bandwidth_range()
301 …range->max_target_bpp_x16 = calc_dsc_bpp_x16(range->stream_kbps, timing->pix_clk_100hz, dsc_caps->… in get_dsc_bandwidth_range()
305 range->min_kbps = dsc_div_by_10_round_up(min_bpp * timing->pix_clk_100hz); in get_dsc_bandwidth_range()
326 const struct dc_crtc_timing *timing, in decide_dsc_target_bpp_x16() argument
335 dsc_common_caps, timing, &range); in decide_dsc_target_bpp_x16()
346 …*target_bpp_x16 = calc_dsc_bpp_x16(target_bandwidth_kbps, timing->pix_clk_100hz, dsc_common_caps->… in decide_dsc_target_bpp_x16()
500 * timing - The stream timing to fit into 'target_bandwidth_kbps' or apply
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| /Linux-v5.4/drivers/media/i2c/ |
| D | bt819.c | 60 struct timing { struct
70 static struct timing timing_data[] = { argument
164 0x16, 0x07, /* 0x16 Video Timing Polarity in bt819_init()
175 struct timing *timing = &timing_data[(decoder->norm & V4L2_STD_525_60) ? 1 : 0]; in bt819_init() local
178 (((timing->vdelay >> 8) & 0x03) << 6) | in bt819_init()
179 (((timing->vactive >> 8) & 0x03) << 4) | in bt819_init()
180 (((timing->hdelay >> 8) & 0x03) << 2) | in bt819_init()
181 ((timing->hactive >> 8) & 0x03); in bt819_init()
182 init[0x04 * 2 - 1] = timing->vdelay & 0xff; in bt819_init()
183 init[0x05 * 2 - 1] = timing->vactive & 0xff; in bt819_init()
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| /Linux-v5.4/drivers/gpu/drm/amd/display/dc/dce120/ |
| D | dce120_timing_generator.c | 100 /* determine if given timing can be supported by TG */
103 const struct dc_crtc_timing *timing, in dce120_timing_generator_validate_timing() argument
106 uint32_t interlace_factor = timing->flags.INTERLACE ? 2 : 1; in dce120_timing_generator_validate_timing()
108 (timing->v_total - timing->v_addressable - in dce120_timing_generator_validate_timing()
109 timing->v_border_top - timing->v_border_bottom) * in dce120_timing_generator_validate_timing()
115 timing, in dce120_timing_generator_validate_timing()
121 timing->h_sync_width < tg110->min_h_sync_width || in dce120_timing_generator_validate_timing()
122 timing->v_sync_width < tg110->min_v_sync_width) in dce120_timing_generator_validate_timing()
129 const struct dc_crtc_timing *timing) in dce120_tg_validate_timing() argument
131 return dce120_timing_generator_validate_timing(tg, timing, SIGNAL_TYPE_NONE); in dce120_tg_validate_timing()
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