| /Linux-v5.10/drivers/gpu/drm/tegra/ |
| D | mipi-phy.c | 1 // SPDX-License-Identifier: GPL-2.0-only
9 #include "mipi-phy.h"
12 * Default D-PHY timings based on MIPI D-PHY specification. Derived from the
13 * valid ranges specified in Section 6.9, Table 14, Page 40 of the D-PHY
16 int mipi_dphy_timing_get_default(struct mipi_dphy_timing *timing, in mipi_dphy_timing_get_default() argument
19 timing->clkmiss = 0; in mipi_dphy_timing_get_default()
20 timing->clkpost = 70 + 52 * period; in mipi_dphy_timing_get_default()
21 timing->clkpre = 8; in mipi_dphy_timing_get_default()
22 timing->clkprepare = 65; in mipi_dphy_timing_get_default()
23 timing->clksettle = 95; in mipi_dphy_timing_get_default()
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| /Linux-v5.10/drivers/gpu/drm/msm/dsi/phy/ |
| D | dsi_phy.c | 1 // SPDX-License-Identifier: GPL-2.0-only
11 (((n) >= 0) ? (((n) + (d) - 1) / (d)) : (((n) - (d) + 1) / (d)))
18 v = (tmax - tmin) * percent; in linear_inter()
21 return max_t(s32, min_result, v - 1); in linear_inter()
26 static void dsi_dphy_timing_calc_clk_zero(struct msm_dsi_dphy_timing *timing, in dsi_dphy_timing_calc_clk_zero() argument
33 temp = 300 * coeff - ((timing->clk_prepare >> 1) + 1) * 2 * ui; in dsi_dphy_timing_calc_clk_zero()
34 tmin = S_DIV_ROUND_UP(temp, ui) - 2; in dsi_dphy_timing_calc_clk_zero()
44 temp = (timing->hs_rqst + timing->clk_prepare + clk_z) & 0x7; in dsi_dphy_timing_calc_clk_zero()
45 timing->clk_zero = clk_z + 8 - temp; in dsi_dphy_timing_calc_clk_zero()
48 int msm_dsi_dphy_timing_calc(struct msm_dsi_dphy_timing *timing, in msm_dsi_dphy_timing_calc() argument
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| D | dsi_phy_14nm.c | 1 // SPDX-License-Identifier: GPL-2.0-only
14 struct msm_dsi_dphy_timing *timing, in dsi_14nm_dphy_set_timing() argument
17 void __iomem *base = phy->lane_base; in dsi_14nm_dphy_set_timing()
19 u32 zero = clk_ln ? timing->clk_zero : timing->hs_zero; in dsi_14nm_dphy_set_timing()
20 u32 prepare = clk_ln ? timing->clk_prepare : timing->hs_prepare; in dsi_14nm_dphy_set_timing()
21 u32 trail = clk_ln ? timing->clk_trail : timing->hs_trail; in dsi_14nm_dphy_set_timing()
22 u32 rqst = clk_ln ? timing->hs_rqst_ckln : timing->hs_rqst; in dsi_14nm_dphy_set_timing()
23 u32 prep_dly = clk_ln ? timing->hs_prep_dly_ckln : timing->hs_prep_dly; in dsi_14nm_dphy_set_timing()
24 u32 halfbyte_en = clk_ln ? timing->hs_halfbyte_en_ckln : in dsi_14nm_dphy_set_timing()
25 timing->hs_halfbyte_en; in dsi_14nm_dphy_set_timing()
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| D | dsi_phy_20nm.c | 1 // SPDX-License-Identifier: GPL-2.0-only
10 struct msm_dsi_dphy_timing *timing) in dsi_20nm_dphy_set_timing() argument
12 void __iomem *base = phy->base; in dsi_20nm_dphy_set_timing()
15 DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO(timing->clk_zero)); in dsi_20nm_dphy_set_timing()
17 DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL(timing->clk_trail)); in dsi_20nm_dphy_set_timing()
19 DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE(timing->clk_prepare)); in dsi_20nm_dphy_set_timing()
20 if (timing->clk_zero & BIT(8)) in dsi_20nm_dphy_set_timing()
24 DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT(timing->hs_exit)); in dsi_20nm_dphy_set_timing()
26 DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO(timing->hs_zero)); in dsi_20nm_dphy_set_timing()
28 DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE(timing->hs_prepare)); in dsi_20nm_dphy_set_timing()
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| D | dsi_phy_28nm_8960.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2012-2015, The Linux Foundation. All rights reserved.
12 struct msm_dsi_dphy_timing *timing) in dsi_28nm_dphy_set_timing() argument
14 void __iomem *base = phy->base; in dsi_28nm_dphy_set_timing()
17 DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO(timing->clk_zero)); in dsi_28nm_dphy_set_timing()
19 DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL(timing->clk_trail)); in dsi_28nm_dphy_set_timing()
21 DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE(timing->clk_prepare)); in dsi_28nm_dphy_set_timing()
24 DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT(timing->hs_exit)); in dsi_28nm_dphy_set_timing()
26 DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO(timing->hs_zero)); in dsi_28nm_dphy_set_timing()
28 DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE(timing->hs_prepare)); in dsi_28nm_dphy_set_timing()
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| D | dsi_phy_28nm.c | 1 // SPDX-License-Identifier: GPL-2.0-only
10 struct msm_dsi_dphy_timing *timing) in dsi_28nm_dphy_set_timing() argument
12 void __iomem *base = phy->base; in dsi_28nm_dphy_set_timing()
15 DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO(timing->clk_zero)); in dsi_28nm_dphy_set_timing()
17 DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL(timing->clk_trail)); in dsi_28nm_dphy_set_timing()
19 DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE(timing->clk_prepare)); in dsi_28nm_dphy_set_timing()
20 if (timing->clk_zero & BIT(8)) in dsi_28nm_dphy_set_timing()
24 DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT(timing->hs_exit)); in dsi_28nm_dphy_set_timing()
26 DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO(timing->hs_zero)); in dsi_28nm_dphy_set_timing()
28 DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE(timing->hs_prepare)); in dsi_28nm_dphy_set_timing()
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| D | dsi_phy_10nm.c | 2 * SPDX-License-Identifier: GPL-2.0
13 void __iomem *base = phy->base; in dsi_phy_hw_v3_0_is_pll_on()
24 void __iomem *lane_base = phy->lane_base; in dsi_phy_hw_v3_0_config_lpcdrx()
43 void __iomem *lane_base = phy->lane_base; in dsi_phy_hw_v3_0_lane_settings()
45 if (phy->cfg->quirks & V3_0_0_10NM_OLD_TIMINGS_QUIRK) in dsi_phy_hw_v3_0_lane_settings()
80 if (!(phy->cfg->quirks & V3_0_0_10NM_OLD_TIMINGS_QUIRK)) { in dsi_phy_hw_v3_0_lane_settings()
94 struct msm_dsi_dphy_timing *timing = &phy->timing; in dsi_10nm_phy_enable() local
95 void __iomem *base = phy->base; in dsi_10nm_phy_enable()
100 if (msm_dsi_dphy_timing_calc_v3(timing, clk_req)) { in dsi_10nm_phy_enable()
101 DRM_DEV_ERROR(&phy->pdev->dev, in dsi_10nm_phy_enable()
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| /Linux-v5.10/drivers/clk/tegra/ |
| D | clk-tegra124-emc.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * drivers/clk/tegra/clk-emc.c
11 #include <linux/clk-provider.h>
47 * When we change the timing to a timing with a parent that has the same
49 * timing that has a different clock source.
101 val = readl(tegra->clk_regs + CLK_SOURCE_EMC); in emc_recalc_rate()
116 struct emc_timing *timing = NULL; in emc_determine_rate() local
121 for (k = 0; k < tegra->num_timings; k++) { in emc_determine_rate()
122 if (tegra->timings[k].ram_code == ram_code) in emc_determine_rate()
126 for (t = k; t < tegra->num_timings; t++) { in emc_determine_rate()
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| /Linux-v5.10/drivers/gpu/drm/nouveau/nvkm/subdev/bios/ |
| D | timing.c | 26 #include <subdev/bios/timing.h>
33 u32 timing = 0; in nvbios_timingTe() local
37 timing = nvbios_rd32(bios, bit_P.offset + 4); in nvbios_timingTe()
40 timing = nvbios_rd32(bios, bit_P.offset + 8); in nvbios_timingTe()
42 if (timing) { in nvbios_timingTe()
43 *ver = nvbios_rd08(bios, timing + 0); in nvbios_timingTe()
46 *hdr = nvbios_rd08(bios, timing + 1); in nvbios_timingTe()
47 *cnt = nvbios_rd08(bios, timing + 2); in nvbios_timingTe()
48 *len = nvbios_rd08(bios, timing + 3); in nvbios_timingTe()
51 return timing; in nvbios_timingTe()
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| /Linux-v5.10/drivers/memory/tegra/ |
| D | tegra124-emc.c | 1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/clk-provider.h>
486 /* Timing change sequence functions */
491 writel(value, emc->regs + EMC_CCFIFO_DATA); in emc_ccfifo_writel()
492 writel(offset, emc->regs + EMC_CCFIFO_ADDR); in emc_ccfifo_writel()
500 writel(1, emc->regs + EMC_TIMING_CONTROL); in emc_seq_update_timing()
503 value = readl(emc->regs + EMC_STATUS); in emc_seq_update_timing()
509 dev_err(emc->dev, "timing update timed out\n"); in emc_seq_update_timing()
517 writel(0, emc->regs + EMC_AUTO_CAL_INTERVAL); in emc_seq_disable_auto_cal()
520 value = readl(emc->regs + EMC_AUTO_CAL_STATUS); in emc_seq_disable_auto_cal()
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| D | tegra30-emc.c | 1 // SPDX-License-Identifier: GPL-2.0+
5 * Based on downstream driver from NVIDIA and tegra124-emc.c
6 * Copyright (C) 2011-2014 NVIDIA Corporation
9 * Copyright (C) 2019 GRATE-DRIVER project
362 writel_relaxed(EMC_TIMING_UPDATE, emc->regs + EMC_TIMING_CONTROL); in emc_seq_update_timing()
364 err = readl_relaxed_poll_timeout_atomic(emc->regs + EMC_STATUS, val, in emc_seq_update_timing()
368 dev_err(emc->dev, "failed to update timing: %d\n", err); in emc_seq_update_timing()
381 status = readl_relaxed(emc->regs + EMC_INTSTATUS) & intmask; in tegra_emc_isr()
387 dev_err_ratelimited(emc->dev, in tegra_emc_isr()
391 writel_relaxed(status, emc->regs + EMC_INTSTATUS); in tegra_emc_isr()
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| D | tegra20-emc.c | 1 // SPDX-License-Identifier: GPL-2.0
167 status = readl_relaxed(emc->regs + EMC_INTSTATUS) & intmask; in tegra_emc_isr()
173 dev_err_ratelimited(emc->dev, in tegra_emc_isr()
177 writel_relaxed(status, emc->regs + EMC_INTSTATUS); in tegra_emc_isr()
185 struct emc_timing *timing = NULL; in tegra_emc_find_timing() local
188 for (i = 0; i < emc->num_timings; i++) { in tegra_emc_find_timing()
189 if (emc->timings[i].rate >= rate) { in tegra_emc_find_timing()
190 timing = &emc->timings[i]; in tegra_emc_find_timing()
195 if (!timing) { in tegra_emc_find_timing()
196 dev_err(emc->dev, "no timing for rate %lu\n", rate); in tegra_emc_find_timing()
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| /Linux-v5.10/drivers/devfreq/ |
| D | rk3399_dmc.c | 1 // SPDX-License-Identifier: GPL-2.0-only
4 * Author: Lin Huang <hl@rock-chips.com>
7 #include <linux/arm-smccc.h>
11 #include <linux/devfreq-event.h>
65 struct dram_timing timing; member
79 unsigned long old_clk_rate = dmcfreq->rate; in rk3399_dmcfreq_target()
93 if (dmcfreq->rate == target_rate) in rk3399_dmcfreq_target()
96 mutex_lock(&dmcfreq->lock); in rk3399_dmcfreq_target()
98 if (dmcfreq->regmap_pmu) { in rk3399_dmcfreq_target()
99 if (target_rate >= dmcfreq->odt_dis_freq) in rk3399_dmcfreq_target()
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| /Linux-v5.10/drivers/video/fbdev/ |
| D | gbefb.c | 4 * Copyright (C) 1999 Silicon Graphics, Inc. - Jeffrey Newquist
5 * Copyright (C) 2002 Vivien Chappelier <vivien.chappelier@linux-mips.org>
14 #include <linux/dma-mapping.h>
37 struct gbe_timing_info timing; member
44 /* macro for fastest write-though access to the framebuffer */
63 #define TILE_MASK (TILE_SIZE - 1)
87 /* 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock) */
102 .height = -1,
103 .width = -1,
133 .height = -1,
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| /Linux-v5.10/drivers/gpu/drm/msm/disp/dpu1/ |
| D | dpu_encoder_phys_vid.c | 1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
13 (e) && (e)->parent ? \
14 (e)->parent->base.id : -1, \
15 (e) && (e)->hw_intf ? \
16 (e)->hw_intf->idx - INTF_0 : -1, ##__VA_ARGS__)
19 (e) && (e)->parent ? \
20 (e)->parent->base.id : -1, \
21 (e) && (e)->hw_intf ? \
22 (e)->hw_intf->idx - INTF_0 : -1, ##__VA_ARGS__)
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| /Linux-v5.10/drivers/video/fbdev/via/ |
| D | via_modesetting.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
4 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
12 #include <linux/via-core.h>
18 void via_set_primary_timing(const struct via_display_timing *timing) in via_set_primary_timing() argument
22 raw.hor_total = timing->hor_total / 8 - 5; in via_set_primary_timing()
23 raw.hor_addr = timing->hor_addr / 8 - 1; in via_set_primary_timing()
24 raw.hor_blank_start = timing->hor_blank_start / 8 - 1; in via_set_primary_timing()
25 raw.hor_blank_end = timing->hor_blank_end / 8 - 1; in via_set_primary_timing()
26 raw.hor_sync_start = timing->hor_sync_start / 8; in via_set_primary_timing()
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| /Linux-v5.10/drivers/gpu/drm/sti/ |
| D | sti_awg_utils.c | 1 // SPDX-License-Identifier: GPL-2.0
11 #define AWG_DELAY (-5)
48 if (fwparams->instruction_offset >= AWG_MAX_INST) { in awg_generate_instr()
50 return -EINVAL; in awg_generate_instr()
57 arg--; /* pixel adjustment */ in awg_generate_instr()
58 arg_tmp--; in awg_generate_instr()
105 return -EINVAL; in awg_generate_instr()
108 arg_tmp = arg_tmp - arg; in awg_generate_instr()
113 fwparams->ram_code[fwparams->instruction_offset] = in awg_generate_instr()
115 fwparams->instruction_offset++; in awg_generate_instr()
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| /Linux-v5.10/drivers/gpu/drm/amd/display/dc/dce110/ |
| D | dce110_timing_generator_v.c | 42 tg->ctx->logger
45 * DCE11 Timing Generator Implementation
65 dm_write_reg(tg->ctx, in dce110_timing_generator_v_enable_crtc()
70 dm_write_reg(tg->ctx, mmCRTCV_MASTER_UPDATE_MODE, value); in dce110_timing_generator_v_enable_crtc()
75 dm_write_reg(tg->ctx, in dce110_timing_generator_v_enable_crtc()
85 value = dm_read_reg(tg->ctx, in dce110_timing_generator_v_disable_crtc()
91 dm_write_reg(tg->ctx, in dce110_timing_generator_v_disable_crtc()
95 * tg->funcs->disable_stereo(tg); in dce110_timing_generator_v_disable_crtc()
103 uint32_t value = dm_read_reg(tg->ctx, addr); in dce110_timing_generator_v_blank_crtc()
117 dm_write_reg(tg->ctx, addr, value); in dce110_timing_generator_v_blank_crtc()
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| /Linux-v5.10/drivers/media/rc/img-ir/ |
| D | img-ir-hw.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 * Copyright 2010-2014 Imagination Technologies Ltd.
12 #include <media/rc-core.h>
18 #define IMG_IR_CODETYPE_BIPHASE 0x2 /* RC-5/6 */
19 #define IMG_IR_CODETYPE_2BITPULSEPOS 0x3 /* RC-MM */
22 /* Timing information */
25 * struct img_ir_control - Decoder control settings
53 * struct img_ir_timing_range - range of timing values
54 * @min: Minimum timing value
55 * @max: Maximum timing value (if < @min, this will be set to @min during
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| /Linux-v5.10/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ |
| D | ramnv50.c | 34 #include <subdev/bios/timing.h>
71 #define T(t) cfg->timing_10_##t
73 nv50_ram_timing_calc(struct nv50_ram *ram, u32 *timing) in nv50_ram_timing_calc() argument
75 struct nvbios_ramcfg *cfg = &ram->base.target.bios; in nv50_ram_timing_calc()
76 struct nvkm_subdev *subdev = &ram->base.fb->subdev; in nv50_ram_timing_calc()
77 struct nvkm_device *device = subdev->device; in nv50_ram_timing_calc()
86 switch ((!T(CWL)) * ram->base.type) { in nv50_ram_timing_calc()
88 T(CWL) = T(CL) - 1; in nv50_ram_timing_calc()
96 if (device->chipset == 0xa0) { in nv50_ram_timing_calc()
97 unkt3b = 0x19 + ram->base.next->bios.rammap_00_16_40; in nv50_ram_timing_calc()
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| /Linux-v5.10/drivers/gpu/drm/amd/display/dc/dsc/ |
| D | dc_dsc.c | 41 const struct dc_crtc_timing *timing) in dc_dsc_bandwidth_in_kbps_from_timing() argument
46 if (timing->flags.DSC) { in dc_dsc_bandwidth_in_kbps_from_timing()
47 kbps = (timing->pix_clk_100hz * timing->dsc_cfg.bits_per_pixel); in dc_dsc_bandwidth_in_kbps_from_timing()
52 switch (timing->display_color_depth) { in dc_dsc_bandwidth_in_kbps_from_timing()
77 kbps = timing->pix_clk_100hz / 10; in dc_dsc_bandwidth_in_kbps_from_timing()
80 if (timing->flags.Y_ONLY != 1) { in dc_dsc_bandwidth_in_kbps_from_timing()
83 if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420) in dc_dsc_bandwidth_in_kbps_from_timing()
85 else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) in dc_dsc_bandwidth_in_kbps_from_timing()
217 dm_error("%s: DPCD DSC bits-per-pixel increment not recognized.\n", __func__); in dsc_bpp_increment_div_from_dpcd()
234 if (!dsc->ctx->dc->debug.disable_dsc) in get_dsc_enc_caps()
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| /Linux-v5.10/Documentation/devicetree/bindings/mmc/ |
| D | sdhci-am654.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: "http://devicetree.org/schemas/mmc/sdhci-am654.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
11 - Ulf Hansson <ulf.hansson@linaro.org>
14 - $ref: mmc-controller.yaml#
19 - ti,am654-sdhci-5.1
20 - ti,j721e-sdhci-8bit
21 - ti,j721e-sdhci-4bit
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| /Linux-v5.10/drivers/ide/ |
| D | triflex.c | 1 // SPDX-License-Identifier: GPL-2.0-only
7 * Copyright (C) 2002 Hewlett-Packard Development Group, L.P.
27 struct pci_dev *dev = to_pci_dev(hwif->dev); in triflex_set_mode()
29 u16 timing = 0; in triflex_set_mode() local
30 u8 channel_offset = hwif->channel ? 0x74 : 0x70, unit = drive->dn & 1; in triflex_set_mode()
34 switch (drive->dma_mode) { in triflex_set_mode()
36 timing = 0x0103; in triflex_set_mode()
39 timing = 0x0203; in triflex_set_mode()
42 timing = 0x0808; in triflex_set_mode()
47 timing = 0x0f0f; in triflex_set_mode()
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| /Linux-v5.10/drivers/ata/ |
| D | pata_triflex.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * pata_triflex.c - Compaq PATA for new ATA layer
15 * Copyright (C) 2002 Hewlett-Packard Development Group, L.P.
36 * triflex_prereset - probe begin
50 struct ata_port *ap = link->ap; in triflex_prereset()
51 struct pci_dev *pdev = to_pci_dev(ap->host->dev); in triflex_prereset()
53 if (!pci_test_config_bits(pdev, &triflex_enable_bits[ap->port_no])) in triflex_prereset()
54 return -ENOENT; in triflex_prereset()
62 * triflex_load_timing - timing configuration
75 struct pci_dev *pdev = to_pci_dev(ap->host->dev); in triflex_load_timing()
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| /Linux-v5.10/Documentation/driver-api/memory-devices/ |
| D | ti-gpmc.rst | 1 .. SPDX-License-Identifier: GPL-2.0
14 * Pseudo-SRAM devices
20 GPMC generic timing calculation:
29 generic timing routine was developed to achieve above requirements.
37 happen that timing as specified by peripheral datasheet is not present
38 in timing structure, in this scenario, try to correlate peripheral
39 timing to the one available. If that doesn't work, try to add a new
40 field as required by peripheral, educate generic timing routine to
45 Generic timing routine has been verified to work properly on
48 A word of caution: generic timing routine has been developed based
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