| /Linux-v6.1/include/uapi/drm/ |
| D | i810_drm.h | 85 /* Texture state (per tex unit)
165 /* Maintain an LRU of contiguous regions of texture space. If
166 * you think you own a region of texture memory, and it has an
172 * texture information of other clients - by maintaining them
175 * texture space, and can make informed decisions as to which
177 * kick out your own texture or someone else's - simply eject
183 int texAge; /* last time texture was uploaded */
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| D | mga_drm.h | 154 /* Setup registers for each texture unit
223 /* LRU lists for texture memory in agp space and on the card.
309 * \name AGP texture region
312 * be filled in with the actual AGP texture settings.
321 __u32 texture_size; /**< Size of the AGP texture region. */
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| D | vc4_drm.h | 112 /* Pointer to uniform data and texture handles for the textures
117 * uniform data has a __u32 index into bo_handles per texture
119 * the program. Following the texture BO handle indices is the actual
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| D | r128_drm.h | 120 /* Texture state */
140 /* Setup registers for each texture unit
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| D | savage_drm.h | 54 /* LRU lists for texture memory in agp space and on the card.
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| D | via_drm.h | 190 int texAge; /* last time texture was uploaded */
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| /Linux-v6.1/drivers/staging/media/atomisp/pci/isp/kernels/bnr/bnr2_2/ |
| D | ia_css_bnr2_2_types.h | 63 s32 detail_gain; /** Gain for low contrast texture control */
64 s32 detail_gain_divisor; /** Gain divisor for low contrast texture control */
65 s32 detail_level_offset; /** Bias value for low contrast texture control */
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| /Linux-v6.1/drivers/gpu/drm/radeon/ |
| D | radeon_drv.h | 75 * Add texture rectangle support for r100.
87 * 1.15- Add support for texture micro tiling
90 * texture filtering on r200
99 * 1.22- Add support for texture cache flushes (R300_TX_CNTL)
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| D | r600_cs.c | 1460 * @texture: texture's bo structure
1467 * the texture and mipmap bo object are big enough to cover this resource.
1470 struct radeon_bo *texture, in r600_check_texture_resource() argument
1546 dev_warn(p->dev, "this kernel doesn't support %d texture dim\n", G_038000_DIM(word0)); in r600_check_texture_resource()
1550 dev_warn(p->dev, "%s:%d texture invalid format %d\n", in r600_check_texture_resource()
1581 dev_warn(p->dev, "texture blevel %d > llevel %d\n", in r600_check_texture_resource()
1593 /* using get ib will give us the offset into the texture bo */ in r600_check_texture_resource()
1594 if ((l0_size + word2) > radeon_bo_size(texture)) { in r600_check_texture_resource()
1595 dev_warn(p->dev, "texture bo too small ((%d %d) (%d %d) %d %d %d -> %d have %ld)\n", in r600_check_texture_resource()
1598 l0_size, radeon_bo_size(texture)); in r600_check_texture_resource()
[all …]
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| D | r300_reg.h | 232 * mode, the swizzling pattern is e.g. used to set zw components in texture
626 * TC_CNT is the number of incoming texture coordinate sets (i.e. it depends
641 /* Only used for texture coordinates.
642 * Use the source field to route texture coordinate input from the
791 /* BEGIN: Texture specification */
794 * The texture specification dwords are grouped by meaning and not by texture
795 * unit. This means that e.g. the offset for texture image unit N is found in
965 /* END: Texture specification */
970 * There are separate instruction streams for texture instructions and ALU
1029 * As far as I can tell, texture instructions cannot write into output
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| D | evergreen_cs.c | 753 struct radeon_bo *texture, in evergreen_cs_track_validate_texture() argument
792 dev_warn(p->dev, "%s:%d texture invalid format %d\n", in evergreen_cs_track_validate_texture()
813 dev_warn(p->dev, "%s:%d texture invalid dimension %d\n", in evergreen_cs_track_validate_texture()
818 r = evergreen_surface_value_conv_check(p, &surf, "texture"); in evergreen_cs_track_validate_texture()
827 r = evergreen_surface_check(p, &surf, "texture"); in evergreen_cs_track_validate_texture()
829 dev_warn(p->dev, "%s:%d texture invalid 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n", in evergreen_cs_track_validate_texture()
835 /* check texture size */ in evergreen_cs_track_validate_texture()
837 dev_warn(p->dev, "%s:%d texture bo base %ld not aligned with %ld\n", in evergreen_cs_track_validate_texture()
851 if (toffset > radeon_bo_size(texture)) { in evergreen_cs_track_validate_texture()
852 dev_warn(p->dev, "%s:%d texture bo too small (layer size %d, " in evergreen_cs_track_validate_texture()
[all …]
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| /Linux-v6.1/Documentation/devicetree/bindings/media/ |
| D | renesas,imr.yaml | 15 capture data or data in an external memory as 2D texture data and performing
16 texture mapping and drawing with respect to any shape that is split into
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| /Linux-v6.1/drivers/staging/media/atomisp/pci/isp/kernels/tdf/tdf_1.0/ |
| D | ia_css_tdf_types.h | 38 s32 eps_scale_text; /** Epsilon scaling coefficient for texture region. */
43 s32 blend_text; /** Blending ratio at texture region. */
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| /Linux-v6.1/drivers/gpu/drm/via/ |
| D | via_3d_reg.h | 670 /* Texture subtype definitions
676 /* Texture subtype definitions
682 /* Attribute of texture n
1031 /* Video Texture */
1045 *-- Define the input texture.
1141 /*=* John Sheng [2003.7.18] texture combine *=*/
1170 *-- Define the texture alpha input.
1244 /* Texture Palette n
1412 /*---- start of texture 0 setting ----
1486 /*---- end of texture 0 setting ---- 0x008f
[all …]
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| D | via_dri1.c | 67 unsigned texture; member
674 * Require that all AGP texture levels reside in the same AGP map which should
695 cur_seq->tex_level_lo[cur_seq->texture]; in finish_current_sequence()
696 unsigned end = cur_seq->tex_level_hi[cur_seq->texture]; in finish_current_sequence()
708 &(cur_seq->t_addr[tex = cur_seq->texture][start]); in finish_current_sequence()
727 ("AGP texture is not in allowed map\n"); in finish_current_sequence()
820 tmp_addr = &cur_seq->t_addr[cur_seq->texture][tmp]; in investigate_hazard()
827 tmp_addr = &cur_seq->t_addr[cur_seq->texture][tmp]; in investigate_hazard()
836 cur_seq->tex_level_lo[tmp = cur_seq->texture] = cmd & 0x3F; in investigate_hazard()
844 cur_seq->pitch[cur_seq->texture][tmp] = in investigate_hazard()
[all …]
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| /Linux-v6.1/drivers/gpu/drm/vc4/ |
| D | vc4_validate.c | 177 * never have a render target larger than 4096. The texture in vc4_check_tex_size()
675 DRM_DEBUG("Texture format %d unsupported\n", type); in reloc_tex()
695 /* The mipmap levels are stored before the base of the texture. Make in reloc_tex()
748 DRM_INFO("Texture p0 at %d: 0x%08x\n", sample->p_offset[0], p0); in reloc_tex()
749 DRM_INFO("Texture p1 at %d: 0x%08x\n", sample->p_offset[1], p1); in reloc_tex()
750 DRM_INFO("Texture p2 at %d: 0x%08x\n", sample->p_offset[2], p2); in reloc_tex()
751 DRM_INFO("Texture p3 at %d: 0x%08x\n", sample->p_offset[3], p3); in reloc_tex()
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| D | vc4_drv.h | 741 * struct vc4_texture_sample_info - saves the offsets into the UBO for texture
744 * This will be used at draw time to relocate the reference to the texture
751 * See the VC4 3D architecture guide page 41 ("Texture and Memory Lookup Unit
752 * Setup") for definitions of the texture parameters.
766 * and validate the shader state record's uniforms that define the texture
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| D | vc4_validate_shaders.c | 31 * (reading it as a texture, uniform data, or direct-addressed TMU
35 * accesses are appropriately bounded, and recording where texture
207 /* Make sure that this texture load is an add of the base in check_tmu_write()
250 "texture setup.\n"); in check_tmu_write()
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| /Linux-v6.1/drivers/char/agp/ |
| D | Kconfig | 14 If you need more texture memory than you can get with the AGP GART
17 and have up to a couple gigs of texture space.
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| /Linux-v6.1/drivers/gpu/drm/v3d/ |
| D | v3d_gem.c | 23 /* Set OVRTMUOUT, which means that the texture sampler uniform in v3d_init_core()
25 * using the hardware default behavior based on the texture in v3d_init_core()
27 * "2" in the indirect texture state's output_type field. in v3d_init_core()
163 /* Invalidates texture L2 cachelines */
181 /* Cleans texture L1 and L2 cachelines (writing back dirty data).
858 * v3d_submit_tfu_ioctl() - Submits a TFU (texture formatting) job to the V3D.
956 * v3d_submit_csd_ioctl() - Submits a CSD (texture formatting) job to the V3D.
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| /Linux-v6.1/drivers/gpu/drm/savage/ |
| D | savage_drv.h | 323 /* texture enable bits (needed for tex addr checking) */
330 * All texture registers and DrawLocalCtrl are local. All other
335 * All texture registers are local. DrawCtrl and ZBufCtrl are
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| D | savage_state.c | 151 /* if any texture regs were changed ... */ in savage_verify_state_s3d()
154 /* ... check texture state */ in savage_verify_state_s3d()
183 /* if any texture regs were changed ... */ in savage_verify_state_s4()
186 /* ... check texture state */ in savage_verify_state_s4()
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| /Linux-v6.1/drivers/gpu/drm/vmwgfx/ |
| D | vmw_surface_cache.h | 327 * @num_layers: Number of slices in an array texture or number of faces in
328 * a cubemap texture.
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| /Linux-v6.1/drivers/gpu/drm/i915/ |
| D | i915_scheduler_types.h | 41 * (e.g. we have to wait until the pixels have been rendering into a texture
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| /Linux-v6.1/Documentation/devicetree/bindings/clock/ |
| D | samsung,exynos850-clock.yaml | 208 - description: Image Texture Processing core clock (from CMU_TOP)
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