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Searched +full:tegra194 +full:- +full:p2u (Results 1 – 11 of 11) sorted by relevance

/Linux-v6.1/Documentation/devicetree/bindings/pci/
Dnvidia,tegra194-pcie-ep.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/nvidia,tegra194-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra194 (and later) PCIe Endpoint controller (Synopsys DesignWare Core based)
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Vidya Sagar <vidyas@nvidia.com>
16 inherits all the common properties defined in snps,dw-pcie-ep.yaml. Some
20 On Tegra194, controllers C0, C4 and C5 support Endpoint mode.
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Dnvidia,tegra194-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/nvidia,tegra194-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra194 (and later) PCIe controller (Synopsys DesignWare Core based)
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Vidya Sagar <vidyas@nvidia.com>
16 inherits all the common properties defined in snps,dw-pcie.yaml. Some of
20 See nvidia,tegra194-pcie-ep.yaml for details on the Endpoint mode device
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/Linux-v6.1/Documentation/devicetree/bindings/phy/
Dphy-tegra194-p2u.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: "http://devicetree.org/schemas/phy/phy-tegra194-p2u.yaml#"
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
7 title: NVIDIA Tegra194 & Tegra234 P2U binding
10 - Thierry Reding <treding@nvidia.com>
13 Tegra194 has two PHY bricks namely HSIO (High Speed IO) and NVHS (NVIDIA High
14 Speed) each interfacing with 12 and 8 P2U instances respectively.
16 each interfacing with 8, 8 and 8 P2U instances respectively.
17 A P2U instance is a glue logic between Synopsys DesignWare Core PCIe IP's PIPE
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/Linux-v6.1/drivers/phy/tegra/
Dphy-tegra194-p2u.c1 // SPDX-License-Identifier: GPL-2.0+
3 * P2U (PIPE to UPHY) driver for Tegra T194 SoC
5 * Copyright (C) 2019-2022 NVIDIA Corporation.
46 writel_relaxed(value, phy->base + reg); in p2u_writel()
51 return readl_relaxed(phy->base + reg); in p2u_readl()
59 if (phy->skip_sz_protection_en) { in tegra_p2u_power_on()
79 if (phy->of_data->one_dir_search) { in tegra_p2u_power_on()
96 struct device *dev = &pdev->dev; in tegra_p2u_probe()
102 return -ENOMEM; in tegra_p2u_probe()
104 phy->of_data = in tegra_p2u_probe()
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DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
12 be called phy-tegra-xusb.
15 tristate "NVIDIA Tegra194 PIPE2UPHY PHY driver"
19 Enable this to support the P2U (PIPE to UPHY) that is part of Tegra 19x SOCs.
DMakefile1 # SPDX-License-Identifier: GPL-2.0-only
2 obj-$(CONFIG_PHY_TEGRA_XUSB) += phy-tegra-xusb.o
4 phy-tegra-xusb-y += xusb.o
5 phy-tegra-xusb-$(CONFIG_ARCH_TEGRA_124_SOC) += xusb-tegra124.o
6 phy-tegra-xusb-$(CONFIG_ARCH_TEGRA_132_SOC) += xusb-tegra124.o
7 phy-tegra-xusb-$(CONFIG_ARCH_TEGRA_210_SOC) += xusb-tegra210.o
8 phy-tegra-xusb-$(CONFIG_ARCH_TEGRA_186_SOC) += xusb-tegra186.o
9 phy-tegra-xusb-$(CONFIG_ARCH_TEGRA_194_SOC) += xusb-tegra186.o
10 obj-$(CONFIG_PHY_TEGRA194_P2U) += phy-tegra194-p2u.o
/Linux-v6.1/arch/arm64/boot/dts/nvidia/
Dtegra194.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra194-clock.h>
3 #include <dt-bindings/gpio/tegra194-gpio.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mailbox/tegra186-hsp.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
7 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
8 #include <dt-bindings/power/tegra194-powergate.h>
9 #include <dt-bindings/reset/tegra194-reset.h>
10 #include <dt-bindings/thermal/tegra194-bpmp-thermal.h>
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Dtegra234.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/clock/tegra234-clock.h>
4 #include <dt-bindings/gpio/tegra234-gpio.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/mailbox/tegra186-hsp.h>
7 #include <dt-bindings/memory/tegra234-mc.h>
8 #include <dt-bindings/power/tegra234-powergate.h>
9 #include <dt-bindings/reset/tegra234-reset.h>
13 interrupt-parent = <&gic>;
14 #address-cells = <2>;
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Dtegra194-p2972-0000.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/linux-event-codes.h>
5 #include <dt-bindings/input/gpio-keys.h>
7 #include "tegra194-p2888.dtsi"
11 compatible = "nvidia,p2972-0000", "nvidia,tegra194";
17 dma-controller@2930000 {
21 interrupt-controller@2a40000 {
29 #address-cells = <1>;
30 #size-cells = <0>;
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Dtegra234-p3737-0000+p3701-0000.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/linux-event-codes.h>
5 #include <dt-bindings/input/gpio-keys.h>
7 #include "tegra234-p3701-0000.dtsi"
8 #include "tegra234-p3737-0000.dtsi"
12 compatible = "nvidia,p3737-0000+p3701-0000", "nvidia,p3701-0000", "nvidia,tegra234";
28 #address-cells = <1>;
29 #size-cells = <0>;
35 remote-endpoint = <&admaif0>;
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/Linux-v6.1/drivers/pci/controller/dwc/
Dpcie-tegra194.c1 // SPDX-License-Identifier: GPL-2.0+
4 * Tegra194
7 * Copyright (C) 2019-2022 NVIDIA Corporation.
35 #include "pcie-designware.h"
37 #include <soc/tegra/bpmp-abi.h>
300 writel_relaxed(value, pcie->appl_base + reg); in appl_writel()
305 return readl_relaxed(pcie->appl_base + reg); in appl_readl()
320 * NOTE:- Since this scenario is uncommon and link as such is not in apply_bad_link_workaround()
322 * transitioning to Gen-2 speed in apply_bad_link_workaround()
324 val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA); in apply_bad_link_workaround()
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