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Searched +full:tegra186 +full:- +full:mc (Results 1 – 9 of 9) sorted by relevance

/Linux-v5.15/drivers/memory/tegra/
DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 tegra-mc-y := mc.o
4 tegra-mc-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20.o
5 tegra-mc-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30.o
6 tegra-mc-$(CONFIG_ARCH_TEGRA_114_SOC) += tegra114.o
7 tegra-mc-$(CONFIG_ARCH_TEGRA_124_SOC) += tegra124.o
8 tegra-mc-$(CONFIG_ARCH_TEGRA_132_SOC) += tegra124.o
9 tegra-mc-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210.o
10 tegra-mc-$(CONFIG_ARCH_TEGRA_186_SOC) += tegra186.o
11 tegra-mc-$(CONFIG_ARCH_TEGRA_194_SOC) += tegra186.o tegra194.o
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Dtegra186.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2017-2021 NVIDIA CORPORATION. All rights reserved.
13 #include <soc/tegra/mc.h>
16 #include <dt-bindings/memory/tegra186-mc.h>
23 static void tegra186_mc_program_sid(struct tegra_mc *mc) in tegra186_mc_program_sid() argument
27 for (i = 0; i < mc->soc->num_clients; i++) { in tegra186_mc_program_sid()
28 const struct tegra_mc_client *client = &mc->soc->clients[i]; in tegra186_mc_program_sid()
31 override = readl(mc->regs + client->regs.sid.override); in tegra186_mc_program_sid()
32 security = readl(mc->regs + client->regs.sid.security); in tegra186_mc_program_sid()
34 dev_dbg(mc->dev, "client %s: override: %x security: %x\n", in tegra186_mc_program_sid()
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Dmc.c1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <linux/dma-mapping.h>
21 #include "mc.h"
25 { .compatible = "nvidia,tegra20-mc-gart", .data = &tegra20_mc_soc },
28 { .compatible = "nvidia,tegra30-mc", .data = &tegra30_mc_soc },
31 { .compatible = "nvidia,tegra114-mc", .data = &tegra114_mc_soc },
34 { .compatible = "nvidia,tegra124-mc", .data = &tegra124_mc_soc },
37 { .compatible = "nvidia,tegra132-mc", .data = &tegra132_mc_soc },
40 { .compatible = "nvidia,tegra210-mc", .data = &tegra210_mc_soc },
43 { .compatible = "nvidia,tegra186-mc", .data = &tegra186_mc_soc },
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/Linux-v5.15/arch/arm64/boot/dts/nvidia/
Dtegra186.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra186-clock.h>
3 #include <dt-bindings/gpio/tegra186-gpio.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mailbox/tegra186-hsp.h>
6 #include <dt-bindings/memory/tegra186-mc.h>
7 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
8 #include <dt-bindings/power/tegra186-powergate.h>
9 #include <dt-bindings/reset/tegra186-reset.h>
10 #include <dt-bindings/thermal/tegra186-bpmp-thermal.h>
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Dtegra194.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra194-clock.h>
3 #include <dt-bindings/gpio/tegra194-gpio.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mailbox/tegra186-hsp.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
7 #include <dt-bindings/power/tegra194-powergate.h>
8 #include <dt-bindings/reset/tegra194-reset.h>
9 #include <dt-bindings/thermal/tegra194-bpmp-thermal.h>
10 #include <dt-bindings/memory/tegra194-mc.h>
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/Linux-v5.15/Documentation/devicetree/bindings/memory-controllers/
Dnvidia,tegra186-mc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra186-mc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra186 (and later) SoC Memory Controller
10 - Jon Hunter <jonathanh@nvidia.com>
11 - Thierry Reding <thierry.reding@gmail.com>
14 The NVIDIA Tegra186 SoC features a 128 bit memory controller that is split
15 into four 32 bit channels to support LPDDR4 with x16 subpartitions. The MC
16 handles memory requests for 40-bit virtual addresses from internal clients
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/Linux-v5.15/include/soc/tegra/
Dmc.h1 /* SPDX-License-Identifier: GPL-2.0-only */
12 #include <linux/interconnect-provider.h>
14 #include <linux/reset-controller.h>
32 * Tegra SMMU, whereas on Tegra186 and later this is the ID used to override the ARM SMMU
57 /* stream ID overrides (Tegra186 and later) */
101 struct tegra_mc *mc);
106 struct tegra_mc *mc) in tegra_smmu_probe() argument
117 struct gart_device *tegra_gart_probe(struct device *dev, struct tegra_mc *mc);
122 tegra_gart_probe(struct device *dev, struct tegra_mc *mc) in tegra_gart_probe() argument
124 return ERR_PTR(-ENODEV); in tegra_gart_probe()
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/Linux-v5.15/Documentation/devicetree/bindings/display/tegra/
Dnvidia,tegra20-host1x.txt4 - compatible: "nvidia,tegra<chip>-host1x"
5 - reg: Physical base address and length of the controller's registers.
6 For pre-Tegra186, one entry describing the whole register area.
7 For Tegra186, one entry for each entry in reg-names:
8 "vm" - VM region assigned to Linux
9 "hypervisor" - Hypervisor region (only if Linux acts as hypervisor)
10 - interrupts: The interrupt outputs from the controller.
11 - #address-cells: The number of cells used to represent physical base addresses
13 - #size-cells: The number of cells used to represent the size of an address
15 - ranges: The mapping of the host1x address space to the CPU address space.
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/Linux-v5.15/drivers/clk/tegra/
Dclk-tegra210.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2012-2020 NVIDIA CORPORATION. All rights reserved.
8 #include <linux/clk-provider.h>
17 #include <dt-bindings/clock/tegra210-car.h>
18 #include <dt-bindings/reset/tegra210-car.h>
23 #include "clk-id.h"
264 * SDM fractional divisor is 16-bit 2's complement signed number within
265 * (-2^12 ... 2^12-1) range. Represented in PLL data structure as unsigned
266 * 16-bit value, with "0" divisor mapped to 0xFFFF. Data "0" is used to
275 #define sdin_get_n_eff(cfg) ((cfg)->n * PLL_SDM_COEFF + ((cfg)->sdm_data ? \
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