| /Linux-v6.1/drivers/phy/ti/ |
| D | phy-dm816x-usb.c | 1 // SPDX-License-Identifier: GPL-2.0-only
15 #include <linux/phy/phy.h>
18 #include <linux/mfd/syscon.h>
23 * phy as being SR70LX Synopsys USB 2.0 OTG nanoPHY. It also seems at
33 * Finally, the phy on dm814x and am335x is different from dm816x.
35 #define DM816X_USB_CTRL_PHYCLKSRC BIT(8) /* 1 = PLL ref clock */
36 #define DM816X_USB_CTRL_PHYSLEEP1 BIT(1) /* Enable the first phy */
37 #define DM816X_USB_CTRL_PHYSLEEP0 BIT(0) /* Enable the second phy */
44 struct regmap *syscon; member
47 struct clk *refclk; member
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| D | phy-ti-pipe3.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * phy-ti-pipe3 - PIPE3 PHY driver.
5 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
12 #include <linux/phy/phy.h>
19 #include <linux/phy/omap_control_phy.h>
21 #include <linux/mfd/syscon.h>
171 struct clk *refclk; member
177 unsigned int dpll_reset_reg; /* reg. index within syscon */
178 unsigned int power_reg; /* power reg. index within syscon */
179 unsigned int pcie_pcs_reg; /* pcs reg. index in syscon */
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| D | phy-am654-serdes.c | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2018 - 2019 Texas Instruments Incorporated - http://www.ti.com/
9 #include <dt-bindings/phy/phy.h>
11 #include <linux/clk-provider.h>
14 #include <linux/mfd/syscon.h>
17 #include <linux/phy/phy.h>
107 /* CMU PLL Control */
142 /* Mid-speed initial calibration control */
145 /* High-speed initial calibration control */
148 /* Mid-speed recalibration control */
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| /Linux-v6.1/Documentation/devicetree/bindings/usb/ |
| D | ti,am62-usb.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/usb/ti,am62-usb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI's AM62 wrapper module for the Synopsys USBSS-DRD controller
10 - Aswath Govindraju <a-govindraju@ti.com>
14 const: ti,am62-usb
21 power-domains:
25 Documentation/devicetree/bindings/soc/ti/sci-pm-domain.yaml
32 clock-names:
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| /Linux-v6.1/drivers/usb/dwc3/ |
| D | dwc3-am62.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * dwc3-am62.c - TI specific Glue layer for AM62 DWC3 USB Controller
5 * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com
12 #include <linux/mfd/syscon.h>
43 /* PHY CONFIG register bits */
87 /* Mask for PHY PLL REFCLK */
97 struct regmap *syscon; member
120 return readl((data->usbss) + offset); in dwc3_ti_readl()
125 writel(value, (data->usbss) + offset); in dwc3_ti_writel()
130 struct device *dev = data->dev; in phy_syscon_pll_refclk()
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| /Linux-v6.1/Documentation/devicetree/bindings/phy/ |
| D | ti,phy-j721e-wiz.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: "http://devicetree.org/schemas/phy/ti,phy-j721e-wiz.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
11 - Kishon Vijay Abraham I <kishon@ti.com>
16 - ti,j721e-wiz-16g
17 - ti,j721e-wiz-10g
18 - ti,am64-wiz-10g
19 - ti,j7200-wiz-10g
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| D | qcom,qusb2-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: "http://devicetree.org/schemas/phy/qcom,qusb2-phy.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
8 title: Qualcomm QUSB2 phy controller
11 - Wesley Cheng <quic_wcheng@quicinc.com>
19 - items:
20 - enum:
21 - qcom,ipq8074-qusb2-phy
22 - qcom,msm8953-qusb2-phy
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| /Linux-v6.1/arch/mips/boot/dts/brcm/ |
| D | bcm63268.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
3 #include "dt-bindings/clock/bcm63268-clock.h"
4 #include "dt-bindings/reset/bcm63268-reset.h"
5 #include "dt-bindings/soc/bcm63268-pm.h"
8 #address-cells = <1>;
9 #size-cells = <1>;
13 #address-cells = <1>;
14 #size-cells = <0>;
16 mips-hpt-frequency = <200000000>;
32 periph_osc: periph-osc {
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| D | bcm6362.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
3 #include "dt-bindings/clock/bcm6362-clock.h"
4 #include "dt-bindings/reset/bcm6362-reset.h"
5 #include "dt-bindings/soc/bcm6362-pm.h"
8 #address-cells = <1>;
9 #size-cells = <1>;
13 #address-cells = <1>;
14 #size-cells = <0>;
16 mips-hpt-frequency = <200000000>;
32 periph_osc: periph-osc {
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| D | bcm6328.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
3 #include "dt-bindings/clock/bcm6328-clock.h"
4 #include "dt-bindings/reset/bcm6328-reset.h"
5 #include "dt-bindings/soc/bcm6328-pm.h"
8 #address-cells = <1>;
9 #size-cells = <1>;
13 #address-cells = <1>;
14 #size-cells = <0>;
16 mips-hpt-frequency = <160000000>;
32 periph_osc: periph-osc {
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| /Linux-v6.1/drivers/phy/rockchip/ |
| D | phy-rockchip-pcie.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Rockchip PCIe PHY driver
5 * Copyright (C) 2016 Shawn Lin <shawn.lin@rock-chips.com>
12 #include <linux/mfd/syscon.h>
17 #include <linux/phy/phy.h>
23 * The higher 16-bit of this register is used for write protection
69 struct phy *phy; member
82 phys[inst->index]); in to_pcie_phy()
85 static struct phy *rockchip_pcie_phy_of_xlate(struct device *dev, in rockchip_pcie_phy_of_xlate()
90 if (args->args_count == 0) in rockchip_pcie_phy_of_xlate()
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| D | phy-rockchip-naneng-combphy.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Rockchip PIPE USB3.0 PCIE SATA Combo Phy driver
8 #include <dt-bindings/phy/phy.h>
10 #include <linux/mfd/syscon.h>
12 #include <linux/phy/phy.h>
22 /* COMBO PHY REG */
133 struct phy *phy; member
138 struct clk *refclk; member
146 temp = readl(priv->mmio + reg); in rockchip_combphy_updatel()
148 writel(temp, priv->mmio + reg); in rockchip_combphy_updatel()
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| /Linux-v6.1/drivers/phy/freescale/ |
| D | phy-fsl-imx8m-pcie.c | 1 // SPDX-License-Identifier: GPL-2.0+
11 #include <linux/mfd/syscon.h>
12 #include <linux/mfd/syscon/imx7-iomuxc-gpr.h>
14 #include <linux/phy/phy.h>
19 #include <dt-bindings/phy/phy-imx8-pcie.h>
53 struct phy *phy; member
62 static int imx8_pcie_phy_power_on(struct phy *phy) in imx8_pcie_phy_power_on() argument
66 struct imx8_pcie_phy *imx8_phy = phy_get_drvdata(phy); in imx8_pcie_phy_power_on()
68 reset_control_assert(imx8_phy->reset); in imx8_pcie_phy_power_on()
70 pad_mode = imx8_phy->refclk_pad_mode; in imx8_pcie_phy_power_on()
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| /Linux-v6.1/drivers/phy/marvell/ |
| D | phy-mvebu-a3700-utmi.c | 1 // SPDX-License-Identifier: GPL-2.0
9 * Marvell A3700 UTMI PHY driver
14 #include <linux/mfd/syscon.h>
17 #include <linux/phy/phy.h>
21 /* Armada 3700 UTMI PHY registers */
59 * struct mvebu_a3700_utmi_caps - PHY capabilities
61 * @usb32: Flag indicating which PHY is in use (impacts the register map):
62 * - The UTMI PHY wired to the USB3/USB2 controller (otg)
63 * - The UTMI PHY wired to the USB2 controller (host only)
64 * @ops: PHY operations
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| D | phy-mvebu-a3700-comphy.c | 1 // SPDX-License-Identifier: GPL-2.0
11 * Structure inspired from phy-mvebu-cp110-comphy.c written by Antoine Tenart.
20 #include <linux/mfd/syscon.h>
22 #include <linux/phy.h>
23 #include <linux/phy/phy.h>
35 /* SATA and USB3 PHY offset compared to SATA PHY */
39 * When accessing common PHY lane registers directly, we need to shift by 1,
40 * since the registers are 16-bit.
174 * This register is not from PHY lane register space. It only exists in the
175 * indirect register space, before the actual PHY lane 2 registers. So the
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| D | phy-mvebu-cp110-comphy.c | 1 // SPDX-License-Identifier: GPL-2.0
5 * Antoine Tenart <antoine.tenart@free-electrons.com>
8 #include <linux/arm-smccc.h>
12 #include <linux/mfd/syscon.h>
14 #include <linux/phy.h>
15 #include <linux/phy/phy.h>
19 /* Relative to priv->base */
107 /* Relative to priv->regmap */
129 * [ 1- 0]: COMPHY polarity invertion
130 * [ 2- 7]: COMPHY speed
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| /Linux-v6.1/arch/arm/boot/dts/ |
| D | arm-realview-pbx.dtsi | 23 #include <dt-bindings/interrupt-controller/irq.h>
24 #include <dt-bindings/gpio/gpio.h>
27 #address-cells = <1>;
28 #size-cells = <1>;
29 compatible = "arm,realview-pbx";
49 vmmc: regulator-vmmc {
50 compatible = "regulator-fixed";
51 regulator-name = "vmmc";
52 regulator-min-microvolt = <3300000>;
53 regulator-max-microvolt = <3300000>;
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| D | arm-realview-pb11mp.dts | 23 /dts-v1/;
24 #include <dt-bindings/interrupt-controller/irq.h>
25 #include <dt-bindings/gpio/gpio.h>
28 #address-cells = <1>;
29 #size-cells = <1>;
31 compatible = "arm,realview-pb11mp";
52 #address-cells = <1>;
53 #size-cells = <0>;
54 enable-method = "arm,realview-smp";
60 next-level-cache = <&L2>;
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| /Linux-v6.1/drivers/phy/intel/ |
| D | phy-intel-lgm-combo.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Intel Combo-PHY driver
5 * Copyright (C) 2019-2020 Intel Corporation.
11 #include <linux/mfd/syscon.h>
15 #include <linux/phy/phy.h>
20 #include <dt-bindings/phy/phy.h>
37 #define COMBO_PHY_ID(x) ((x)->parent->id)
38 #define PHY_ID(x) ((x)->id)
80 struct phy *phy; member
107 struct intel_combo_phy *cbphy = iphy->parent; in intel_cbphy_iphy_enable()
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| /Linux-v6.1/drivers/ufs/host/ |
| D | ufs-mediatek.c | 1 // SPDX-License-Identifier: GPL-2.0
9 #include <linux/arm-smccc.h>
17 #include <linux/phy/phy.h>
25 #include "ufshcd-pltfrm.h"
28 #include "ufs-mediatek.h"
31 #include "ufs-mediatek-trace.h"
45 { .compatible = "mediatek,mt8183-ufshci" },
53 "PHY Adapter Layer",
61 "PHY error on Lane 0",
62 "PHY error on Lane 1",
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