| /Linux-v5.15/drivers/pci/controller/cadence/ |
| D | pci-j721e.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * pci-j721e - PCIe controller driver for TI's J721E SoCs
5 * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com
15 #include <linux/mfd/syscon.h>
24 #include "pcie-cadence.h"
56 u32 mode; member
70 enum j721e_pcie_mode mode; member
77 static inline u32 j721e_pcie_user_readl(struct j721e_pcie *pcie, u32 offset) in j721e_pcie_user_readl() argument
79 return readl(pcie->user_cfg_base + offset); in j721e_pcie_user_readl()
82 static inline void j721e_pcie_user_writel(struct j721e_pcie *pcie, u32 offset, in j721e_pcie_user_writel() argument
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| /Linux-v5.15/Documentation/devicetree/bindings/pci/ |
| D | ti-pci.txt | 3 PCIe DesignWare Controller
4 - compatible: Should be "ti,dra7-pcie" for RC (deprecated)
5 Should be "ti,dra7-pcie-ep" for EP (deprecated)
6 Should be "ti,dra746-pcie-rc" for dra74x/dra76 in RC mode
7 Should be "ti,dra746-pcie-ep" for dra74x/dra76 in EP mode
8 Should be "ti,dra726-pcie-rc" for dra72x in RC mode
9 Should be "ti,dra726-pcie-ep" for dra72x in EP mode
10 - phys : list of PHY specifiers (used by generic PHY framework)
11 - phy-names : must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the
13 - ti,hwmods : Name of the hwmod associated to the pcie, "pcie<X>",
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| D | ti,am65-pci-host.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: http://devicetree.org/schemas/pci/ti,am65-pci-host.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Kishon Vijay Abraham I <kishon@ti.com>
14 - $ref: /schemas/pci/pci-bus.yaml#
19 - ti,am654-pcie-rc
20 - ti,keystone-pcie
25 reg-names:
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| D | ti,am65-pci-ep.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: http://devicetree.org/schemas/pci/ti,am65-pci-ep.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Kishon Vijay Abraham I <kishon@ti.com>
14 - $ref: pci-ep.yaml#
19 - ti,am654-pcie-ep
24 reg-names:
26 - const: app
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| D | axis,artpec6-pcie.txt | 1 * Axis ARTPEC-6 PCIe interface
3 This PCIe host controller is based on the Synopsys DesignWare PCIe IP
4 and thus inherits all the common properties defined in snps,dw-pcie.yaml.
7 - compatible: "axis,artpec6-pcie", "snps,dw-pcie" for ARTPEC-6 in RC mode;
8 "axis,artpec6-pcie-ep", "snps,dw-pcie" for ARTPEC-6 in EP mode;
9 "axis,artpec7-pcie", "snps,dw-pcie" for ARTPEC-7 in RC mode;
10 "axis,artpec7-pcie-ep", "snps,dw-pcie" for ARTPEC-7 in EP mode;
11 - reg: base addresses and lengths of the PCIe controller (DBI),
13 - reg-names: Must include the following entries:
14 - "dbi"
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| D | ti,j721e-pci-ep.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: "http://devicetree.org/schemas/pci/ti,j721e-pci-ep.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
8 title: TI J721E PCI EP (PCIe Wrapper)
11 - Kishon Vijay Abraham I <kishon@ti.com>
14 - $ref: "cdns-pcie-ep.yaml#"
19 - const: ti,j721e-pcie-ep
20 - description: PCIe EP controller in AM64
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| D | ti,j721e-pci-host.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: "http://devicetree.org/schemas/pci/ti,j721e-pci-host.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
8 title: TI J721E PCI Host (PCIe Wrapper)
11 - Kishon Vijay Abraham I <kishon@ti.com>
14 - $ref: "cdns-pcie-host.yaml#"
19 - const: ti,j721e-pcie-host
20 - description: PCIe controller in AM64
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| /Linux-v5.15/Documentation/devicetree/bindings/phy/ |
| D | lantiq,vrx200-pcie-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/lantiq,vrx200-pcie-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Lantiq VRX200 and ARX300 PCIe PHY Device Tree Bindings
10 - Martin Blumenstingl <martin.blumenstingl@googlemail.com>
13 "#phy-cells":
15 description: selects the PHY mode as defined in <dt-bindings/phy/phy-lantiq-vrx200-pcie.h>
19 - lantiq,vrx200-pcie-phy
20 - lantiq,arx300-pcie-phy
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| D | rockchip-pcie-phy.txt | 1 Rockchip PCIE PHY
2 -----------------------
5 - compatible: rockchip,rk3399-pcie-phy
6 - clocks: Must contain an entry in clock-names.
7 See ../clocks/clock-bindings.txt for details.
8 - clock-names: Must be "refclk"
9 - resets: Must contain an entry in reset-names.
11 - reset-names: Must be "phy"
13 Required properties for legacy PHY mode (deprecated):
14 - #phy-cells: must be 0
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| D | samsung-phy.txt | 2 -------------------------------------------------
5 - compatible : should be one of the listed compatibles:
6 - "samsung,s5pv210-mipi-video-phy"
7 - "samsung,exynos5420-mipi-video-phy"
8 - "samsung,exynos5433-mipi-video-phy"
9 - #phy-cells : from the generic phy bindings, must be 1;
12 - syscon - phandle to the PMU system controller
15 - samsung,pmu-syscon - phandle to the PMU system controller
16 - samsung,disp-sysreg - phandle to the DISP system registers controller
17 - samsung,cam0-sysreg - phandle to the CAM0 system registers controller
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| D | phy-ocelot-serdes.txt | 2 -------------------------------------
8 One specific SerDes can also be used as a PCIe interface.
10 Hence, a SerDes represents an interface, be it an Ethernet or a PCIe one.
13 half/full-duplex and 1000Mbps in full-duplex mode while SERDES6G supports
14 10/100Mbps in half/full-duplex and 1000/2500Mbps in full-duplex mode.
19 This is a child of the HSIO syscon ("mscc,ocelot-hsio", see
24 - compatible: should be "mscc,vsc7514-serdes"
25 - #phy-cells : from the generic phy bindings, must be 2.
28 defined in dt-bindings/phy/phy-ocelot-serdes.h
33 compatible = "mscc,vsc7514-serdes";
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| D | phy-hi3798cv200-combphy.txt | 1 HiSilicon STB PCIE/SATA/USB3 PHY
4 - compatible: Should be "hisilicon,hi3798cv200-combphy"
5 - reg: Should be the address space for COMBPHY configuration and state
8 - #phy-cells: Should be 1. The cell number is used to select the phy mode
9 as defined in <dt-bindings/phy/phy.h>.
10 - clocks: The phandle to clock provider and clock specifier pair.
11 - resets: The phandle to reset controller and reset specifier pair.
13 Refer to phy/phy-bindings.txt for the generic PHY binding properties.
16 - hisilicon,fixed-mode: If the phy device doesn't support mode select
17 but a fixed mode setting, the property should be present to specify
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| /Linux-v5.15/drivers/pci/controller/dwc/ |
| D | pci-dra7xx.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * pcie-dra7xx - PCIe controller driver for TI DRA7xx SoCs
5 * Copyright (C) 2013-2014 Texas Instruments Incorporated - https://www.ti.com
27 #include <linux/mfd/syscon.h>
32 #include "pcie-designware.h"
34 /* PCIe controller wrapper DRA7XX configuration registers */
90 int phy_count; /* DT phy-names count */
93 enum dw_pcie_device_mode mode; member
97 enum dw_pcie_device_mode mode; member
101 #define to_dra7xx_pcie(x) dev_get_drvdata((x)->dev)
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| D | pci-keystone.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe host controller driver for Texas Instruments Keystone SoCs
5 * Copyright (C) 2013-2014 Texas Instruments., Ltd.
8 * Author: Murali Karicheri <m-karicheri2@ti.com>
9 * Implementation based on pci-exynos.c and pcie-designware.c
19 #include <linux/mfd/syscon.h>
32 #include "pcie-designware.h"
55 #define PCIE_LEGACY_IRQ_ENABLE_SET(n) (0x188 + (0x10 * ((n) - 1)))
56 #define PCIE_LEGACY_IRQ_ENABLE_CLR(n) (0x18c + (0x10 * ((n) - 1)))
80 #define ERR_NONFATAL BIT(2) /* Non-fatal error */
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| D | pcie-artpec6.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe host controller driver for Axis ARTPEC-6 SoC
20 #include <linux/mfd/syscon.h>
23 #include "pcie-designware.h"
25 #define to_artpec6_pcie(x) dev_get_drvdata((x)->dev)
34 struct regmap *regmap; /* DT axis,syscon-pcie */
37 enum dw_pcie_device_mode mode; member
42 enum dw_pcie_device_mode mode; member
47 /* ARTPEC-6 specific registers */
61 /* ARTPEC-7 specific fields */
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| /Linux-v5.15/drivers/staging/mt7621-dts/ |
| D | mt7621.dtsi | 1 #include <dt-bindings/interrupt-controller/mips-gic.h>
2 #include <dt-bindings/gpio/gpio.h>
3 #include <dt-bindings/clock/mt7621-clk.h>
6 #address-cells = <1>;
7 #size-cells = <1>;
8 compatible = "mediatek,mt7621-soc";
21 #address-cells = <0>;
22 #interrupt-cells = <1>;
23 interrupt-controller;
24 compatible = "mti,cpu-interrupt-controller";
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| /Linux-v5.15/arch/arm64/boot/dts/ti/ |
| D | k3-am65-main.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/
7 #include <dt-bindings/phy/phy-am654-serdes.h>
11 compatible = "mmio-sram";
13 #address-cells = <1>;
14 #size-cells = <1>;
17 atf-sram@0 {
21 sysfw-sram@f0000 {
25 l3cache-sram@100000 {
30 gic500: interrupt-controller@1800000 {
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| /Linux-v5.15/arch/arm64/boot/dts/marvell/ |
| D | armada-37xx.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
25 reserved-memory {
26 #address-cells = <2>;
27 #size-cells = <2>;
34 psci-area@4000000 {
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| /Linux-v5.15/Documentation/devicetree/bindings/soc/rockchip/ |
| D | grf.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Heiko Stuebner <heiko@sntech.de>
15 - items:
16 - enum:
17 - rockchip,rk3288-sgrf
18 - rockchip,rv1108-usbgrf
19 - const: syscon
20 - items:
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| /Linux-v5.15/arch/arm/boot/dts/ |
| D | dra74x.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2014 Texas Instruments Incorporated - https://www.ti.com/
16 compatible = "arm,cortex-a15";
18 operating-points-v2 = <&cpu0_opp_table>;
21 clock-names = "cpu";
23 clock-latency = <300000>; /* From omap-cpufreq driver */
26 #cooling-cells = <2>; /* min followed by max */
28 vbb-supply = <&abb_mpu>;
40 compatible = "arm,cortex-a15-pmu";
41 interrupt-parent = <&wakeupgen>;
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| /Linux-v5.15/drivers/phy/ti/ |
| D | phy-ti-pipe3.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * phy-ti-pipe3 - PIPE3 PHY driver.
5 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
21 #include <linux/mfd/syscon.h>
177 unsigned int dpll_reset_reg; /* reg. index within syscon */
178 unsigned int power_reg; /* power reg. index within syscon */
179 unsigned int pcie_pcs_reg; /* pcs reg. index in syscon */
181 enum pipe3_mode mode; member
206 enum pipe3_mode mode; member
212 .mode = PIPE3_MODE_USBSS,
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| /Linux-v5.15/drivers/phy/st/ |
| D | phy-spear1340-miphy.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * ST spear1340-miphy driver
12 #include <linux/dma-mapping.h>
14 #include <linux/mfd/syscon.h>
32 /* PCIE - SATA configuration registers */
34 /* PCIE CFG MASks */
76 PCIE, enumerator
80 /* phy mode: 0 for SATA 1 for PCIe */
81 enum spear1340_miphy_mode mode; member
90 regmap_update_bits(priv->misc, SPEAR1340_PCIE_SATA_CFG, in spear1340_miphy_sata_init()
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| D | phy-spear1310-miphy.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * ST SPEAr1310-miphy driver
12 #include <linux/dma-mapping.h>
14 #include <linux/mfd/syscon.h>
97 PCIE, enumerator
103 /* phy mode: 0 for SATA 1 for PCIe */
104 enum spear1310_miphy_mode mode; member
115 regmap_update_bits(priv->misc, SPEAR1310_PCIE_MIPHY_CFG_1, in spear1310_miphy_pcie_init()
119 switch (priv->id) { in spear1310_miphy_pcie_init()
130 return -EINVAL; in spear1310_miphy_pcie_init()
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| /Linux-v5.15/arch/arm64/boot/dts/hisilicon/ |
| D | hip06.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 compatible = "hisilicon,hip06-d03";
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 compatible = "arm,psci-0.2";
22 #address-cells = <1>;
23 #size-cells = <0>;
25 cpu-map {
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| /Linux-v5.15/arch/arm64/boot/dts/socionext/ |
| D | uniphier-pxs3.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/gpio/uniphier-gpio.h>
10 #include <dt-bindings/thermal/thermal.h>
13 compatible = "socionext,uniphier-pxs3";
14 #address-cells = <2>;
15 #size-cells = <2>;
16 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <0>;
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