| /Linux-v6.6/drivers/mfd/ |
| D | syscon.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
11 #include <linux/clk.h>
20 #include <linux/platform_data/syscon.h>
24 #include <linux/mfd/syscon.h>
32 struct syscon { struct
45 static struct syscon *of_syscon_register(struct device_node *np, bool check_res) in of_syscon_register() argument
47 struct clk *clk; in of_syscon_register() local
48 struct syscon *syscon; in of_syscon_register() local
57 syscon = kzalloc(sizeof(*syscon), GFP_KERNEL); in of_syscon_register()
58 if (!syscon) in of_syscon_register()
[all …]
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| /Linux-v6.6/drivers/clk/nxp/ |
| D | clk-lpc18xx-creg.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Clk driver for NXP LPC18xx/43xx Configuration Registers (CREG)
8 #include <linux/clk-provider.h>
11 #include <linux/mfd/syscon.h>
50 ret = regmap_update_bits(creg->reg, LPC18XX_CREG_CREG0, in clk_creg_32k_prepare()
67 regmap_update_bits(creg->reg, LPC18XX_CREG_CREG0, in clk_creg_32k_unprepare()
77 regmap_read(creg->reg, LPC18XX_CREG_CREG0, ®); in clk_creg_32k_is_prepared()
93 return regmap_update_bits(creg->reg, LPC18XX_CREG_CREG0, in clk_creg_enable()
94 creg->en_mask, creg->en_mask); in clk_creg_enable()
101 regmap_update_bits(creg->reg, LPC18XX_CREG_CREG0, in clk_creg_disable()
[all …]
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| /Linux-v6.6/Documentation/devicetree/bindings/clock/ |
| D | sprd,sc9860-clk.txt | 2 ------------------------
5 - compatible: should contain the following compatible strings:
6 - "sprd,sc9860-pmu-gate"
7 - "sprd,sc9860-pll"
8 - "sprd,sc9860-ap-clk"
9 - "sprd,sc9860-aon-prediv"
10 - "sprd,sc9860-apahb-gate"
11 - "sprd,sc9860-aon-gate"
12 - "sprd,sc9860-aonsecure-clk"
13 - "sprd,sc9860-agcp-gate"
[all …]
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| D | pistachio-clock.txt | 6 from the device-tree.
9 ----------------
12 defined with the following clock-output-names:
13 - "xtal": External 52Mhz oscillator (required)
14 - "audio_clk_in": Alternate audio reference clock (optional)
15 - "enet_clk_in": Alternate ethernet PHY clock (optional)
18 ----------------------
21 co-processor), audio, and several peripherals.
24 - compatible: Must be "img,pistachio-clk".
25 - reg: Must contain the base address and length of the core clock controller.
[all …]
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| D | sprd,sc9863a-clk.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/clock/sprd,sc9863a-clk.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Orson Zhai <orsonzhai@gmail.com>
12 - Baolin Wang <baolin.wang7@gmail.com>
13 - Chunyan Zhang <zhang.lyra@gmail.com>
16 "#clock-cells":
21 - sprd,sc9863a-ap-clk
22 - sprd,sc9863a-aon-clk
[all …]
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| /Linux-v6.6/drivers/spi/ |
| D | spi-dw-mmio.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Memory-mapped interface driver for DW SPI Core
8 #include <linux/clk.h>
15 #include <linux/mfd/syscon.h>
24 #include "spi-dw.h"
30 struct clk *clk; member
31 struct clk *pclk;
52 struct regmap *syscon; member
61 * bit: |---3-------2-------1-------0
79 struct dw_spi *dws = spi_controller_get_devdata(spi->controller); in dw_spi_mscc_set_cs()
[all …]
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| /Linux-v6.6/Documentation/devicetree/bindings/net/ |
| D | stm32-dwmac.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/net/stm32-dwmac.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Alexandre Torgue <alexandre.torgue@foss.st.com>
12 - Christophe Roullier <christophe.roullier@foss.st.com>
23 - st,stm32-dwmac
24 - st,stm32mp1-dwmac
26 - compatible
29 - $ref: snps,dwmac.yaml#
[all …]
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| D | starfive,jh7110-dwmac.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/net/starfive,jh7110-dwmac.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Emil Renner Berthing <kernel@esmil.dk>
12 - Samin Guo <samin.guo@starfivetech.com>
19 - starfive,jh7110-dwmac
21 - compatible
26 - enum:
27 - starfive,jh7110-dwmac
[all …]
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| /Linux-v6.6/Documentation/devicetree/bindings/mfd/ |
| D | canaan,k210-sysctl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mfd/canaan,k210-sysctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Damien Le Moal <dlemoal@kernel.org>
20 - const: canaan,k210-sysctl
21 - const: syscon
22 - const: simple-mfd
29 clock-names:
31 - const: pclk
[all …]
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| /Linux-v6.6/Documentation/devicetree/bindings/arm/mediatek/ |
| D | mediatek,imgsys.txt | 8 - compatible: Should be one of:
9 - "mediatek,mt2701-imgsys", "syscon"
10 - "mediatek,mt2712-imgsys", "syscon"
11 - "mediatek,mt6765-imgsys", "syscon"
12 - "mediatek,mt6779-imgsys", "syscon"
13 - "mediatek,mt6797-imgsys", "syscon"
14 - "mediatek,mt7623-imgsys", "mediatek,mt2701-imgsys", "syscon"
15 - "mediatek,mt8167-imgsys", "syscon"
16 - "mediatek,mt8173-imgsys", "syscon"
17 - "mediatek,mt8183-imgsys", "syscon"
[all …]
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| D | mediatek,ipu.txt | 8 - compatible: Should be one of:
9 - "mediatek,mt8183-ipu_conn", "syscon"
10 - "mediatek,mt8183-ipu_adl", "syscon"
11 - "mediatek,mt8183-ipu_core0", "syscon"
12 - "mediatek,mt8183-ipu_core1", "syscon"
13 - #clock-cells: Must be 1
15 The ipu controller uses the common clk binding from
16 Documentation/devicetree/bindings/clock/clock-bindings.txt
17 The available clocks are defined in dt-bindings/clock/mt*-clk.h.
21 ipu_conn: syscon@19000000 {
[all …]
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| D | mediatek,vdecsys.txt | 8 - compatible: Should be one of:
9 - "mediatek,mt2701-vdecsys", "syscon"
10 - "mediatek,mt2712-vdecsys", "syscon"
11 - "mediatek,mt6779-vdecsys", "syscon"
12 - "mediatek,mt6797-vdecsys", "syscon"
13 - "mediatek,mt7623-vdecsys", "mediatek,mt2701-vdecsys", "syscon"
14 - "mediatek,mt8167-vdecsys", "syscon"
15 - "mediatek,mt8173-vdecsys", "syscon"
16 - "mediatek,mt8183-vdecsys", "syscon"
17 - #clock-cells: Must be 1
[all …]
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| D | mediatek,audsys.txt | 8 - compatible: Should be one of:
9 - "mediatek,mt2701-audsys", "syscon"
10 - "mediatek,mt6765-audsys", "syscon"
11 - "mediatek,mt6779-audio", "syscon"
12 - "mediatek,mt7622-audsys", "syscon"
13 - "mediatek,mt7623-audsys", "mediatek,mt2701-audsys", "syscon"
14 - "mediatek,mt8167-audiosys", "syscon"
15 - "mediatek,mt8183-audiosys", "syscon"
16 - "mediatek,mt8192-audsys", "syscon"
17 - "mediatek,mt8516-audsys", "syscon"
[all …]
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| D | mediatek,ethsys.txt | 8 - compatible: Should be:
9 - "mediatek,mt2701-ethsys", "syscon"
10 - "mediatek,mt7622-ethsys", "syscon"
11 - "mediatek,mt7623-ethsys", "mediatek,mt2701-ethsys", "syscon"
12 - "mediatek,mt7629-ethsys", "syscon"
13 - "mediatek,mt7981-ethsys", "syscon"
14 - "mediatek,mt7986-ethsys", "syscon"
15 - #clock-cells: Must be 1
16 - #reset-cells: Must be 1
18 The ethsys controller uses the common clk binding from
[all …]
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| D | mediatek,mfgcfg.txt | 8 - compatible: Should be one of:
9 - "mediatek,mt2712-mfgcfg", "syscon"
10 - "mediatek,mt6779-mfgcfg", "syscon"
11 - "mediatek,mt8167-mfgcfg", "syscon"
12 - "mediatek,mt8183-mfgcfg", "syscon"
13 - #clock-cells: Must be 1
15 The mfgcfg controller uses the common clk binding from
16 Documentation/devicetree/bindings/clock/clock-bindings.txt
17 The available clocks are defined in dt-bindings/clock/mt*-clk.h.
21 mfgcfg: syscon@13000000 {
[all …]
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| D | mediatek,vencsys.txt | 8 - compatible: Should be one of:
9 - "mediatek,mt2712-vencsys", "syscon"
10 - "mediatek,mt6779-vencsys", "syscon"
11 - "mediatek,mt6797-vencsys", "syscon"
12 - "mediatek,mt8173-vencsys", "syscon"
13 - "mediatek,mt8183-vencsys", "syscon"
14 - #clock-cells: Must be 1
16 The vencsys controller uses the common clk binding from
17 Documentation/devicetree/bindings/clock/clock-bindings.txt
18 The available clocks are defined in dt-bindings/clock/mt*-clk.h.
[all …]
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| D | mediatek,mcucfg.txt | 8 - compatible: Should be one of:
9 - "mediatek,mt2712-mcucfg", "syscon"
10 - "mediatek,mt8183-mcucfg", "syscon"
11 - #clock-cells: Must be 1
13 The mcucfg controller uses the common clk binding from
14 Documentation/devicetree/bindings/clock/clock-bindings.txt
15 The available clocks are defined in dt-bindings/clock/mt*-clk.h.
19 mcucfg: syscon@10220000 {
20 compatible = "mediatek,mt2712-mcucfg", "syscon";
22 #clock-cells = <1>;
|
| /Linux-v6.6/drivers/pci/controller/cadence/ |
| D | pci-j721e.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * pci-j721e - PCIe controller driver for TI's J721E SoCs
5 * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com
9 #include <linux/clk.h>
15 #include <linux/mfd/syscon.h>
23 #include "pcie-cadence.h"
54 struct clk *refclk;
78 return readl(pcie->user_cfg_base + offset); in j721e_pcie_user_readl()
84 writel(value, pcie->user_cfg_base + offset); in j721e_pcie_user_writel()
89 return readl(pcie->intd_cfg_base + offset); in j721e_pcie_intd_readl()
[all …]
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| /Linux-v6.6/drivers/clk/versatile/ |
| D | clk-icst.c | 1 // SPDX-License-Identifier: GPL-2.0-only
7 * Copyright (C) 2012-2015 Linus Walleij
17 #include <linux/clk-provider.h>
20 #include <linux/mfd/syscon.h>
23 #include "clk-icst.h"
37 * struct clk_icst - ICST VCO clock wrapper
59 * vco_get() - get ICST VCO settings from a certain ICST
68 ret = regmap_read(icst->map, icst->vcoreg_off, &val); in vco_get()
77 * "Integrator CM926EJ-S, CM946E-S, CM966E-S, CM1026EJ-S and in vco_get()
78 * CM1136JF-S User Guide" ARM DUI 0138E, page 3-13 thru 3-14. in vco_get()
[all …]
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| /Linux-v6.6/arch/arm64/boot/dts/sprd/ |
| D | ums512.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include <dt-bindings/clock/sprd,ums512-clk.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 #address-cells = <2>;
18 #size-cells = <0>;
20 cpu-map {
51 compatible = "arm,cortex-a55";
[all …]
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| /Linux-v6.6/arch/arm/boot/dts/mediatek/ |
| D | mt2701.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/clock/mt2701-clk.h>
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/power/mt2701-power.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/memory/mt2701-larb-port.h>
14 #include <dt-bindings/reset/mt2701-resets.h>
15 #include "mt2701-pinfunc.h"
18 #address-cells = <2>;
[all …]
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| /Linux-v6.6/drivers/video/fbdev/ |
| D | clps711x-fb.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #include <linux/clk.h>
17 #include <linux/mfd/syscon.h>
18 #include <linux/mfd/syscon/clps711x.h>
22 #define CLPS711X_FB_NAME "clps711x-fb"
34 struct clk *clk; member
36 struct regmap *syscon; member
47 struct clps711x_fb_info *cfb = info->par; in clps711x_fb_setcolreg()
50 if (regno >= BIT(info->var.bits_per_pixel)) in clps711x_fb_setcolreg()
51 return -EINVAL; in clps711x_fb_setcolreg()
[all …]
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| /Linux-v6.6/drivers/net/can/c_can/ |
| D | c_can_platform.c | 9 * - Sascha Hauer, Marc Kleine-Budde, Pengutronix <s.hauer@pengutronix.de>
10 * - Simon Kallweit, intefo AG <simon.kallweit@intefo.ch>
33 #include <linux/clk.h>
36 #include <linux/mfd/syscon.h>
47 /* 16-bit c_can registers can be arranged differently in the memory
48 * architecture of different implementations. For example: 16-bit
49 * registers can be aligned to a 16-bit boundary or 32-bit boundary etc.
55 return readw(priv->base + priv->regs[index]); in c_can_plat_read_reg_aligned_to_16bit()
61 writew(val, priv->base + priv->regs[index]); in c_can_plat_write_reg_aligned_to_16bit()
67 return readw(priv->base + 2 * priv->regs[index]); in c_can_plat_read_reg_aligned_to_32bit()
[all …]
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| /Linux-v6.6/arch/arm64/boot/dts/mediatek/ |
| D | mt2712e.dtsi | 5 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include <dt-bindings/clock/mt2712-clk.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/memory/mt2712-larb-port.h>
12 #include <dt-bindings/phy/phy.h>
13 #include <dt-bindings/power/mt2712-power.h>
14 #include "mt2712-pinfunc.h"
18 interrupt-parent = <&sysirq>;
19 #address-cells = <2>;
[all …]
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| /Linux-v6.6/arch/arm64/boot/dts/nuvoton/ |
| D | nuvoton-common-npcm8xx.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
4 #include <dt-bindings/clock/nuvoton,npcm845-clk.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/interrupt-controller/irq.h>
9 #address-cells = <2>;
10 #size-cells = <2>;
11 interrupt-parent = <&gic>;
14 #address-cells = <2>;
15 #size-cells = <2>;
16 compatible = "simple-bus";
[all …]
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