Searched full:synthesised (Results 1 – 4 of 4) sorted by relevance
43 control the duty cycle for channel x have a second "shadow"/buffer reg synthesised.45 synchronised mode for all channels it has been synthesised for.
9 synthesised into an FPGA or CPLD.
8 synthesised with different options that change the behaviour.
1445 * Instrs Sample(n...) are the synthesised samples occurring in cs_etm__sample()2400 * need the tid of the PERF_RECORD_EXIT event to assign to the synthesised samples because in cs_etm__process_event()2416 * for samples so that synthesised samples occur from this point in cs_etm__process_event()
