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/Linux-v6.1/drivers/media/pci/cx18/
Dcx18-irq.c23 static void epu_cmd(struct cx18 *cx, u32 sw1) in epu_cmd() argument
25 if (sw1 & IRQ_CPU_TO_EPU) in epu_cmd()
27 if (sw1 & IRQ_APU_TO_EPU) in epu_cmd()
34 u32 sw1, sw2, hw2; in cx18_irq_handler() local
36 sw1 = cx18_read_reg(cx, SW1_INT_STATUS) & cx->sw1_irq_mask; in cx18_irq_handler()
40 if (sw1) in cx18_irq_handler()
41 cx18_write_reg_expect(cx, sw1, SW1_INT_STATUS, ~sw1, sw1); in cx18_irq_handler()
47 if (sw1 || sw2 || hw2) in cx18_irq_handler()
48 CX18_DEBUG_HI_IRQ("received interrupts SW1: %x SW2: %x HW2: %x\n", in cx18_irq_handler()
49 sw1, sw2, hw2); in cx18_irq_handler()
[all …]
Dcx18-scb.h15 are in the SW1 register. */
107 /* Value to write to register SW1 register set (0xC7003100) after the
/Linux-v6.1/arch/arm64/boot/dts/renesas/
Drzg2lc-smarc.dtsi12 * DIP-Switch SW1 setting on SoM
14 * SW1-2 : SW_SD0_DEV_SEL (1: eMMC; 0: uSD)
15 * SW1-3 : SW_SCIF_CAN (1: CAN1; 0: SCIF1)
16 * SW1-4 : SW_RSPI_CAN (1: CAN1; 0: RSPI1)
17 * SW1-5 : SW_I2S0_I2S1 (1: I2S2 (HDMI audio); 0: I2S0)
18 * Please change below macros according to SW1 setting
83 * SW1 should be at position 2->3 so that SER0_CTS# line is activated
Dr9a07g043u11-smarc.dts11 * DIP-Switch SW1 setting
13 * SW1-2 : SW_SD0_DEV_SEL (0: uSD; 1: eMMC)
14 * SW1-3 : SW_ET0_EN_N (0: ETHER0; 1: CAN0, CAN1, SSI1, RSPI1)
15 * Please change below macros according to SW1 setting on the SoM
Drzg2l-smarc-som.dtsi12 /* SW1[2] should be at position 2/OFF to enable 64 GB eMMC */
17 * SW1[2] should be at position 3/ON.
222 * SD0 device selection is XOR between GPIO_SD0_DEV_SEL and SW1[2]
225 * SW1[2] should be at position 2/OFF to enable 64 GB eMMC
226 * SW1[2] should be at position 3/ON to enable uSD card CN3
Drzg2lc-smarc-som.dtsi147 * SD0 device selection is XOR between GPIO_SD0_DEV_SEL and SW1[2]
150 * SW1[2] should be at OFF position to enable 64 GB eMMC
151 * SW1[2] should be at position ON to enable uSD card CN3
Drzg2l-smarc.dtsi41 * SW1 should be at position 2->3 so that SER0_CTS# line is activated
/Linux-v6.1/Documentation/devicetree/bindings/regulator/
Dltc3676.txt8 - regulators: Contains eight regulator child nodes sw1, sw2, sw3, sw4,
13 nodes for sw1, sw2, sw3, sw4, ldo1, ldo2 and ldo4 additionally need to specify
20 Regulators sw1, sw2, sw3, sw4 can regulate the feedback reference from:
36 sw1_reg: sw1 {
Dltc3589.txt8 - regulators: Contains eight regulator child nodes sw1, sw2, sw3, bb-out,
13 nodes for sw1, sw2, sw3, bb-out, ldo1, and ldo2 additionally need to specify
20 Regulators sw1, sw2, sw3, and ldo2 can regulate the feedback reference from
36 sw1_reg: sw1 {
Dpv88060.txt11 BUCK1, LDO1, LDO2, LDO3, LDO4, LDO5, LDO6, LDO7, SW1, SW2, SW3, SW4,
84 SW1 {
85 regulator-name = "sw1";
/Linux-v6.1/Documentation/networking/
Darcnet-hardware.rst803 < | SW1 | | SW2 | |
829 SW1 1-6: I/O Base Address Select
889 The first six switches in switch group SW1 are used to select one
932 Switches seven through ten of switch group SW1 are used to select the
1063 SW1: DIP-Switches for Station Address
1085 The station address is binary-coded with SW1.
1341 | | 90C65 || SW1 | ____|
1419 The last three switches in switch block SW1 are used to select one
1442 Switches 1-5 of switch block SW1 select the Memory Base address.
1554 < | PROM | | SW1 | A | 2 | ID3
[all …]
/Linux-v6.1/Documentation/hid/
Dhid-alps.rst114 1 0 0 SW6 SW5 SW4 SW3 SW2 SW1
148 SW1-SW6:
164 Byte1 1 1 1 0 1 SW3 SW2 SW1
173 SW1-SW3:
/Linux-v6.1/drivers/staging/r8188eu/include/
Drtl8188e_xmit.h94 ((struct txdesc_88e *)(txdesc))->sw1 = (((value)>>8) & 0x0f); \
125 u8 sw1:4; member
/Linux-v6.1/drivers/media/dvb-frontends/
Ddib0090.h87 extern int dib0090_set_switch(struct dvb_frontend *fe, u8 sw1, u8 sw2, u8 sw3);
157 u8 sw1, u8 sw2, u8 sw3) in dib0090_set_switch() argument
/Linux-v6.1/arch/mips/kernel/
Dbmips_vec.S36 * triggered by the SW1 interrupt. If that is the case we try to move
50 /* re-enable IRQs to wait for SW1 */
66 /* wait here for SW1 interrupt from bmips_boot_secondary() */
/Linux-v6.1/drivers/media/i2c/
Dm52790.c43 u8 sw1 = (state->input | state->output) & 0xff; in m52790_write() local
46 return i2c_smbus_write_byte_data(client, sw1, sw2); in m52790_write()
/Linux-v6.1/Documentation/devicetree/bindings/mfd/
Dmc13xxx.txt86 sw1 : regulator SW1 (register 24, bit 0)
/Linux-v6.1/drivers/regulator/
Dltc3676.c172 /* SW1, SW2, SW3, SW4 linear 0.8V-3.3V with scalar via R1/R2 feeback res */
225 LTC3676_LINEAR_REG(SW1, sw1, BUCK1, DVB1A),
Dltc3589.c131 /* SW1, SW2, SW3, LDO2 */
257 LTC3589_LINEAR_REG(SW1, sw1, B1DTV1),
Dmc13892-regulator.c267 MC13892_SW_DEFINE(SW1, sw1, SWITCHERS0, SWITCHERS0, mc13892_sw1),
418 * According to the MC13892 documentation note 59 (Table 47) the SW1 in mc13892_sw_regulator_get_voltage_sel()
450 * Don't mess with the HI bit or support HI voltage offsets for SW1. in mc13892_sw_regulator_set_voltage_sel()
Dpcap-regulator.c131 VREG_INFO(SW1, PCAP_REG_SWCTRL, 1, 2, NA, NA),
228 VREG(VAUX4), VREG(VSIM), VREG(VSIM2), VREG(VVIB), VREG(SW1), VREG(SW2),
/Linux-v6.1/tools/testing/selftests/net/forwarding/
Dipip_lib.sh9 # SW1 uses default VRF so tunnel has no bound dev.
18 # | SW1 | |
73 # | SW1 | |
/Linux-v6.1/Documentation/devicetree/bindings/gpio/
Dmicrochip,pic32-gpio.txt44 button@sw1 {
/Linux-v6.1/arch/arm/boot/dts/
Dr8a7742-iwg21d-q7-dbcm-ca.dts235 * Set SW1 switch on camera board to 'OFF' as we are using 8bit mode
267 /* Set SW1 switch on the SOM to 'ON' */
/Linux-v6.1/drivers/iio/adc/
Dtwl4030-madc.c121 * @method: RT, SW1, SW2
157 * @requests: Array of request struct corresponding to SW1, SW2 and RT
271 * SW1 and SW2 software conversions also called asynchronous or GPC request.
438 * corresponding to RT, SW1, SW2 conversion requests.
537 * corresponding to RT SW1 or SW2 conversion methods.

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