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/Linux-v6.1/Documentation/devicetree/bindings/usb/
Dusb.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Greg Kroah-Hartman <gregkh@linuxfoundation.org>
22 phy-names:
26 usb-phy:
27 $ref: /schemas/types.yaml#/definitions/phandle-array
36 UTMI+ PHY with an 8- or 16-bit interface if UTMI+ is selected, UTMI+ low
38 serial is specified and High-Speed Inter-Chip feature if HSIC is
44 maximum-speed:
[all …]
Dcdns,usb3.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cadence USBSS-DRD controller bindings
10 - Pawel Laszczak <pawell@cadence.com>
18 - description: OTG controller registers
19 - description: XHCI Host controller registers
20 - description: DEVICE controller registers
22 reg-names:
24 - const: otg
[all …]
Dti,hd3ss3220.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Biju Das <biju.das.jz@bp.renesas.com>
12 description: |-
14 Configuration (CC) logic and 5V VCONN sourcing for ecosystems implementing USB Type-C. The
36 description: Super Speed (SS) MUX inputs connected to SS capable connector.
40 description: Output of 2:1 MUX connected to Super Speed (SS) data bus.
43 - port@0
44 - port@1
[all …]
Dnvidia,tegra-xudc.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: "http://devicetree.org/schemas/usb/nvidia,tegra-xudc.yaml#"
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
14 - Nagarjuna Kristam <nkristam@nvidia.com>
15 - JC Kuo <jckuo@nvidia.com>
16 - Thierry Reding <treding@nvidia.com>
21 - enum:
22 - nvidia,tegra210-xudc # For Tegra210
23 - nvidia,tegra186-xudc # For Tegra186
[all …]
/Linux-v6.1/Documentation/hwmon/
Dnct6775.rst15 Addresses scanned: ISA address retrieved from Super I/O registers
19 * Nuvoton NCT5572D/NCT6771F/NCT6772F/NCT6775F/W83677HG-I
23 Addresses scanned: ISA address retrieved from Super I/O registers
31 Addresses scanned: ISA address retrieved from Super I/O registers
39 Addresses scanned: ISA address retrieved from Super I/O registers
47 Addresses scanned: ISA address retrieved from Super I/O registers
55 Addresses scanned: ISA address retrieved from Super I/O registers
63 Addresses scanned: ISA address retrieved from Super I/O registers
71 Addresses scanned: ISA address retrieved from Super I/O registers
79 Addresses scanned: ISA address retrieved from Super I/O registers
[all …]
Df71882fg.rst10 Addresses scanned: none, address read from Super I/O config space
18 Addresses scanned: none, address read from Super I/O config space
26 Addresses scanned: none, address read from Super I/O config space
34 Addresses scanned: none, address read from Super I/O config space
42 Addresses scanned: none, address read from Super I/O config space
50 Addresses scanned: none, address read from Super I/O config space
58 Addresses scanned: none, address read from Super I/O config space
66 Addresses scanned: none, address read from Super I/O config space
74 Addresses scanned: none, address read from Super I/O config space
82 Addresses scanned: none, address read from Super I/O config space
[all …]
Dit87.rst10 Addresses scanned: from Super I/O config space (8 I/O ports)
18 Addresses scanned: from Super I/O config space (8 I/O ports)
24 Addresses scanned: from Super I/O config space (8 I/O ports)
32 Addresses scanned: from Super I/O config space (8 I/O ports)
40 Addresses scanned: from Super I/O config space (8 I/O ports)
48 Addresses scanned: from Super I/O config space (8 I/O ports)
56 Addresses scanned: from Super I/O config space (8 I/O ports)
64 Addresses scanned: from Super I/O config space (8 I/O ports)
72 Addresses scanned: from Super I/O config space (8 I/O ports)
80 Addresses scanned: from Super I/O config space (8 I/O ports)
[all …]
Dw83627ehf.rst10 Addresses scanned: ISA address retrieved from Super I/O registers
18 Addresses scanned: ISA address retrieved from Super I/O registers
22 * Winbond W83627DHG-P
26 Addresses scanned: ISA address retrieved from Super I/O registers
34 Addresses scanned: ISA address retrieved from Super I/O registers
42 Addresses scanned: ISA address retrieved from Super I/O registers
46 * Winbond W83667HG-B
50 Addresses scanned: ISA address retrieved from Super I/O registers
54 * Nuvoton NCT6775F/W83667HG-I
58 Addresses scanned: ISA address retrieved from Super I/O registers
[all …]
Df71805f.rst10 Addresses scanned: none, address read from Super I/O config space
18 Addresses scanned: none, address read from Super I/O config space
26 Addresses scanned: none, address read from Super I/O config space
44 -----------
46 The Fintek F71805F/FG Super I/O chip includes complete hardware monitoring
53 The Fintek F71872F/FG Super I/O chip is almost the same, with two
57 The Fintek F71806F/FG Super-I/O chip is essentially the same as the
65 ------------------
67 Voltages are sampled by an 8-bit ADC with a LSB of 8 mV. The supported
84 in1 VIN1 VTT1.2V 10K - 1.00 1.20 V
[all …]
Dpc87360.rst10 Addresses scanned: none, address read from Super I/O config space
22 -----------------
27 - 0: None
28 - **1**: Forcibly enable internal voltage and temperature channels,
30 - 2: Forcibly enable all voltage and temperature channels, except in9
31 - 3: Forcibly enable all voltage and temperature channels, including in9
42 -----------
44 The National Semiconductor PC87360 Super I/O chip contains monitoring and
48 The National Semiconductor PC87365 and PC87366 Super I/O chips are complete
56 PC87360 - 2 2 - 0xE1
[all …]
Dpc87427.rst10 Addresses scanned: none, address read from Super I/O config space
21 -----------
23 The National Semiconductor Super I/O chip includes complete hardware
36 --------------
38 Fan rotation speeds are reported as 14-bit values from a gated clock
41 An alarm is triggered if the rotation speed drops below a programmable
42 limit. Another alarm is triggered if the speed is too low to be measured
46 Fan Speed Control
47 -----------------
49 Fan speed can be controlled by PWM outputs. There are 4 possible modes:
[all …]
Dsch5627.rst10 Addresses scanned: none, address read from Super I/O config space
18 -----------
20 SMSC SCH5627 Super I/O chips include complete hardware monitoring
24 affect the speed of each fan. Setting pwmX_auto_channels_temp to 0 forces
25 the corresponding fan to full speed until another value is written.
Dsmsc47m1.rst10 Addresses scanned: none, address read from Super I/O config space
26 Addresses scanned: none, address read from Super I/O config space
34 Addresses scanned: none, address read from Super I/O config space
44 - Mark D. Studebaker <mdsxyz123@yahoo.com>,
45 - With assistance from Bruce Allen <ballen@uwm.edu>, and his
48 - http://www.lsc-group.phys.uwm.edu/%7Eballen/driver/
50 - Gabriele Gorla <gorlik@yahoo.com>,
51 - Jean Delvare <jdelvare@suse.de>
54 -----------
56 The Standard Microsystems Corporation (SMSC) 47M1xx Super I/O chips
[all …]
Ddme1737.rst18 Addresses scanned: none, address read from Super-I/O config space
34 Addresses scanned: none, address read from Super-I/O config space
43 -----------------
52 Include non-standard LPC addresses 0x162e and 0x164e
55 - VIA EPIA SN18000
59 -----------
63 and SCH5127 Super-I/O chips. These chips feature monitoring of 3 temp sensors
64 temp[1-3] (2 remote diodes and 1 internal), 8 voltages in[0-7] (7 external and
65 1 internal) and up to 6 fan speeds fan[1-6]. Additionally, the chips implement
66 up to 5 PWM outputs pwm[1-3,5-6] for controlling fan speeds both manually and
[all …]
/Linux-v6.1/drivers/usb/gadget/function/
Du_uvc.h1 /* SPDX-License-Identifier: GPL-2.0 */
7 * Copyright (c) 2013-2014 Samsung Electronics Co., Ltd.
33 * Control descriptors array pointers for full-/high-speed and
34 * super-speed. They point by default to the uvc_fs_control_cls and
42 * Streaming descriptors array pointers for full-speed, high-speed and
43 * super-speed. They will point to the uvc_[fhs]s_streaming_cls arrays
44 * for configfs-based gadgets. Legacy gadgets must initialize them in
51 /* Default control descriptors for configfs-based gadgets. */
58 * Control descriptors pointers arrays for full-/high-speed and
59 * super-speed. The first element is a configurable control header
[all …]
/Linux-v6.1/drivers/usb/common/
Dcommon.c1 // SPDX-License-Identifier: GPL-2.0
7 * compiled-in as well. Otherwise, if either of the two stacks is
29 * usb_ep_type_string() - Returns human readable-name of the endpoint type.
30 * @ep_type: The endpoint type to return human-readable name for. If it's not
70 [USB_SPEED_LOW] = "low-speed",
71 [USB_SPEED_FULL] = "full-speed",
72 [USB_SPEED_HIGH] = "high-speed",
74 [USB_SPEED_SUPER] = "super-speed",
75 [USB_SPEED_SUPER_PLUS] = "super-speed-plus",
80 [USB_SSP_GEN_2x1] = "super-speed-plus-gen2x1",
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/phy/
Dsocionext,uniphier-usb3ss-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/socionext,uniphier-usb3ss-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier USB3 Super-Speed (SS) PHY
12 Although the controller includes High-Speed PHY and Super-Speed PHY,
13 this describes about Super-Speed PHY.
16 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
21 - socionext,uniphier-pro4-usb3-ssphy
22 - socionext,uniphier-pro5-usb3-ssphy
[all …]
Dnvidia,tegra124-xusb-padctl.txt11 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
12 super-speed USB. Other lanes are for various types of low-speed, full-speed
13 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
14 contains a software-configurable mux that sits between the I/O controller
17 In addition to per-lane configuration, USB 3.0 ports may require additional
18 settings on a per-board basis.
20 Pads will be represented as children of the top-level XUSB pad controller
23 PHY bindings, as described by the phy-bindings.txt file in this directory.
34 --------------------
35 - compatible: Must be:
[all …]
/Linux-v6.1/Documentation/driver-api/usb/
Dusb3-debug-port.rst19 3) have a USB 3.0 super-speed A-to-A debugging cable.
30 super-speed port). The debug device is fully compliant with
32 performance full-duplex serial link between the debug target
41 Other uses include simpler, lockless logging instead of a full-
58 "usbcore.autosuspend=-1"
63 should be a USB 3.0 super-speed A-to-A debugging cable.
74 # tail -f /var/log/kern.log
75 [ 1815.983374] usb 4-3: new SuperSpeed USB device number 4 using xhci_hcd
76 [ 1815.999595] usb 4-3: LPM exit latency is zeroed, disabling LPM.
77 [ 1815.999899] usb 4-3: New USB device found, idVendor=1d6b, idProduct=0004
[all …]
/Linux-v6.1/drivers/phy/qualcomm/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
36 Support for the USB PHY-s on Qualcomm IPQ40xx SoC-s.
68 controllers on Qualcomm chips. This driver supports the high-speed
75 depends on EXTCON || !EXTCON # if EXTCON=m, this cannot be built-in
78 Support for the USB high-speed ULPI compliant phy on Qualcomm
86 Enable support for the USB high-speed SNPS Femto phy on Qualcomm
99 tristate "Qualcomm 28nm High-Speed PHY"
101 depends on EXTCON || !EXTCON # if EXTCON=m, this cannot be built-in
105 High-Speed PHY driver. This driver supports the Hi-Speed PHY which
110 tristate "Qualcomm USB Super-Speed PHY driver"
[all …]
/Linux-v6.1/drivers/usb/gadget/udc/
DKconfig1 # SPDX-License-Identifier: GPL-2.0
7 # NOTE: Gadget support ** DOES NOT ** depend on host-side CONFIG_USB !!
9 # - Host systems (like PCs) need CONFIG_USB (with "A" jacks).
10 # - Peripherals (like PDAs) need CONFIG_USB_GADGET (with "B" jacks).
11 # - Some systems have both kinds of controllers.
13 # With help from a special transceiver and a "Mini-AB" jack, systems with
14 # both kinds of controller can also support "USB On-the-Go" (CONFIG_USB_OTG).
22 # - integrated/SOC controllers first
23 # - licensed IP used in both SOC and discrete versions
24 # - discrete ones (including all PCI-only controllers)
[all …]
/Linux-v6.1/arch/arm64/boot/dts/xilinx/
Dzynqmp-zc1751-xm017-dc3.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP zc1751-xm017-dc3
5 * (C) Copyright 2016 - 2021, Xilinx, Inc.
10 /dts-v1/;
13 #include "zynqmp-clk-ccf.dtsi"
14 #include <dt-bindings/phy/phy.h>
17 model = "ZynqMP zc1751-xm017-dc3 RevA";
18 compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
34 stdout-path = "serial0:115200n8";
43 compatible = "fixed-clock";
[all …]
/Linux-v6.1/Documentation/ABI/testing/
Dconfigfs-usb-gadget1 What: /config/usb-gadget
5 This group contains sub-groups corresponding to created
8 What: /config/usb-gadget/gadget
20 max_speed maximum speed the driver supports. Valid
21 names are super-speed-plus, super-speed,
22 high-speed, full-speed, and low-speed.
34 What: /config/usb-gadget/gadget/configs
40 What: /config/usb-gadget/gadget/configs/config
51 What: /config/usb-gadget/gadget/configs/config/strings
55 This group contains subdirectories for language-specific
[all …]
/Linux-v6.1/include/linux/usb/
Dcomposite.h1 // SPDX-License-Identifier: GPL-2.0+
3 * composite.h -- framework for usb gadgets which are composite devices
5 * Copyright (C) 2006-2008 David Brownell
14 * functions within any single configuration, and (b) Multi-configuration
50 * struct usb_os_desc_ext_prop - describes one "Extended Property"
70 * struct usb_os_desc - describes OS descriptors associated with one interface
90 * struct usb_os_desc_table - describes OS descriptors associated with one
105 * struct usb_function - describes one function of a configuration
109 * @fs_descriptors: Table of full (or low) speed descriptors, using interface and
111 * the function will not be available at full speed (or at low speed).
[all …]
/Linux-v6.1/arch/arm64/boot/dts/qcom/
Dsm6350-sony-xperia-lena-pdx213.dts1 // SPDX-License-Identifier: BSD-3-Clause
5 /dts-v1/;
12 chassis-type = "handset";
13 qcom,msm-id = <434 0x10000>, <459 0x10000>;
14 qcom,board-id = <0x1000B 0>;
17 #address-cells = <2>;
18 #size-cells = <2>;
22 compatible = "simple-framebuffer";
36 cd-gpios = <&tlmm 94 GPIO_ACTIVE_HIGH>;
40 gpio-reserved-ranges = <13 4>, <45 2>, <56 2>;
[all …]

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