Searched +full:sun4i +full:- +full:a10 +full:- +full:pll3 +full:- +full:clk (Results 1 – 7 of 7) sorted by relevance
| /Linux-v5.10/Documentation/devicetree/bindings/clock/ |
| D | allwinner,sun4i-a10-pll3-clk.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-pll3-clk.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A10 Video PLL Device Tree Bindings
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
16 "#clock-cells":
20 const: allwinner,sun4i-a10-pll3-clk
28 clock-output-names:
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| D | allwinner,sun4i-a10-tcon-ch0-clk.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-tcon-ch0-clk.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A10 TCON Channel 0 Clock Device Tree Bindings
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
16 "#clock-cells":
19 "#reset-cells":
24 - allwinner,sun4i-a10-tcon-ch0-clk
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| D | allwinner,sun4i-a10-display-clk.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-display-clk.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A10 Display Clock Device Tree Bindings
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
16 "#clock-cells":
19 "#reset-cells":
23 const: allwinner,sun4i-a10-display-clk
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| D | fixed-factor-clock.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/clock/fixed-factor-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Michael Turquette <mturquette@baylibre.com>
11 - Stephen Boyd <sboyd@kernel.org>
16 - allwinner,sun4i-a10-pll3-2x-clk
17 - fixed-factor-clock
19 "#clock-cells":
25 clock-div:
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| /Linux-v5.10/drivers/clk/sunxi/ |
| D | Makefile | 1 # SPDX-License-Identifier: GPL-2.0
3 # Makefile for sunxi specific clk
6 obj-$(CONFIG_CLK_SUNXI) += clk-factors.o
8 obj-$(CONFIG_CLK_SUNXI_CLOCKS) += clk-sunxi.o
9 obj-$(CONFIG_CLK_SUNXI_CLOCKS) += clk-a10-codec.o
10 obj-$(CONFIG_CLK_SUNXI_CLOCKS) += clk-a10-hosc.o
11 obj-$(CONFIG_CLK_SUNXI_CLOCKS) += clk-a10-mod1.o
12 obj-$(CONFIG_CLK_SUNXI_CLOCKS) += clk-a10-pll2.o
13 obj-$(CONFIG_CLK_SUNXI_CLOCKS) += clk-a10-ve.o
14 obj-$(CONFIG_CLK_SUNXI_CLOCKS) += clk-a20-gmac.o
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| D | clk-sun4i-pll3.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Maxime Ripard <maxime.ripard@free-electrons.com>
8 #include <linux/clk-provider.h>
23 const char *clk_name = node->name, *parent; in sun4i_a10_pll3_setup()
28 struct clk *clk; in sun4i_a10_pll3_setup() local
31 of_property_read_string(node, "clock-output-names", &clk_name); in sun4i_a10_pll3_setup()
44 gate->reg = reg; in sun4i_a10_pll3_setup()
45 gate->bit_idx = SUN4I_A10_PLL3_GATE_BIT; in sun4i_a10_pll3_setup()
46 gate->lock = &sun4i_a10_pll3_lock; in sun4i_a10_pll3_setup()
52 mult->reg = reg; in sun4i_a10_pll3_setup()
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| /Linux-v5.10/drivers/clk/ |
| D | clk-fixed-factor.c | 1 // SPDX-License-Identifier: GPL-2.0
6 #include <linux/clk-provider.h>
16 * prepare - clk_prepare only ensures that parents are prepared
17 * enable - clk_enable only ensures that parents are enabled
18 * rate - rate is fixed. clk->rate = parent->rate / div * mult
19 * parent - fixed parent. No clk_set_parent support
28 rate = (unsigned long long int)parent_rate * fix->mult; in clk_factor_recalc_rate()
29 do_div(rate, fix->div); in clk_factor_recalc_rate()
41 best_parent = (rate / fix->mult) * fix->div; in clk_factor_round_rate()
45 return (*prate / fix->div) * fix->mult; in clk_factor_round_rate()
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