Searched +full:sun4i +full:- +full:a10 +full:- +full:pll1 (Results 1 – 4 of 4) sorted by relevance
| /Linux-v5.10/Documentation/devicetree/bindings/clock/ |
| D | allwinner,sun4i-a10-pll1-clk.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-pll1-clk.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A10 CPU PLL Device Tree Bindings
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
16 "#clock-cells":
21 - allwinner,sun4i-a10-pll1-clk
22 - allwinner,sun6i-a31-pll1-clk
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| D | allwinner,sun4i-a10-cpu-clk.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-cpu-clk.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A10 CPU Clock Device Tree Bindings
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
16 "#clock-cells":
20 const: allwinner,sun4i-a10-cpu-clk
30 clock-output-names:
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| /Linux-v5.10/drivers/clk/sunxi/ |
| D | clk-sunxi.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #include <linux/clk-provider.h>
14 #include <linux/reset-controller.h>
19 #include "clk-factors.h"
27 * sun4i_get_pll1_factors() - calculates n, k, m, p factors for PLL1
28 * PLL1 rate is calculated as follows
38 div = req->rate / 6000000; in sun4i_get_pll1_factors()
39 req->rate = 6000000 * div; in sun4i_get_pll1_factors()
41 /* m is always zero for pll1 */ in sun4i_get_pll1_factors()
42 req->m = 0; in sun4i_get_pll1_factors()
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| /Linux-v5.10/Documentation/arm/sunxi/ |
| D | clocks.rst | 20 PLL1
31 PLL1 |
49 A: The linux-sunxi wiki contains a page documenting the clock registers,
52 http://linux-sunxi.org/A10/CCM
57 https://github.com/linux-sunxi/linux-sunxi/tree/sunxi-3.0/arch/arm/mach-sun4i/clock/ccmu
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