| /Linux-v5.15/Documentation/ABI/testing/ |
| D | sysfs-bus-mei | 6 Description: Stores the same MODALIAS value emitted by uevent
13 Description: Stores mei client device name
20 Description: Stores mei client device uuid
27 Description: Stores mei client protocol version
34 Description: Stores mei client maximum number of connections
41 Description: Stores mei client fixed address, if any
48 Description: Stores mei client vtag support status
55 Description: Stores mei client maximum message length
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| D | sysfs-devices-platform-sh_mobile_lcdc_fb | 8 Stores the alpha blending value for the overlay. Values range
32 Stores the x,y overlay position on the display in pixels. The
42 Stores the raster operation (ROP3) for the overlay. Values
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| /Linux-v5.15/Documentation/core-api/ |
| D | refcount-vs-atomic.rst | 42 stores (all po-earlier instructions) on the same CPU are completed
44 It also guarantees that all po-earlier stores on the same CPU
45 and all propagated stores from other CPUs must propagate to all
50 stores (all po-earlier instructions) on the same CPU are completed
52 stores on the same CPU and all propagated stores from other CPUs
58 stores (all po-later instructions) on the same CPU are
60 po-later stores on the same CPU must propagate to all other CPUs
67 then further stores are ordered against this operation.
68 Control dependency on stores are not implemented using any explicit
69 barriers, but rely on CPU not to speculate on stores. This is only
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| /Linux-v5.15/tools/memory-model/Documentation/ |
| D | control-dependencies.txt | 11 One such challenge is that control dependencies order only later stores.
31 However, stores are not speculated. This means that ordering is
43 the compiler might fuse the store to "b" with other stores. Worse yet,
60 identical stores on both branches of the "if" statement as follows:
104 guaranteed only when the stores differ, for example:
212 only to the stores in the then-clause and else-clause of the "if" statement
219 (*) Control dependencies can order prior loads against later stores.
221 Not prior loads against later loads, nor prior stores against
224 stores and later loads, smp_mb().
226 (*) If both legs of the "if" statement contain identical stores to
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| D | explanation.txt | 102 device, stores it in a buffer, and sets a flag to indicate the buffer
134 Thus, P0 stores the data in buf and then sets flag. Meanwhile, P1
140 This pattern of memory accesses, where one CPU stores values to two
197 it, as loads can obtain values only from earlier stores.
202 P1 must load 0 from buf before P0 stores 1 to it; otherwise r2
206 P0 stores 1 to buf before storing 1 to flag, since it executes
222 each CPU stores to its own shared location and then loads from the
270 W: P0 stores 1 to flag executes before
273 Z: P0 stores 1 to buf executes before
274 W: P0 stores 1 to flag.
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| /Linux-v5.15/arch/powerpc/include/asm/ |
| D | barrier.h | 19 * providing an ordering (separately) for (a) cacheable stores and (b)
20 * loads and stores to non-cacheable memory (e.g. I/O devices).
22 * mb() prevents loads and stores being reordered across this point.
24 * wmb() prevents stores being reordered across this point.
32 * doesn't order loads with respect to previous stores. Lwsync can be
107 * pmem_wmb() ensures that all stores for which the modification
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| /Linux-v5.15/arch/ia64/include/asm/ |
| D | barrier.h | 23 * wmb(): Guarantees that all preceding stores to memory-
25 * stores and that all following stores will be
26 * visible only after all previous stores.
52 * IA64 GCC turns volatile stores into st.rel and volatile loads into ld.acq no
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| /Linux-v5.15/arch/mips/include/asm/octeon/ |
| D | octeon.h | 212 * stores; if clear, SYNCWS and SYNCS only order
213 * unmarked stores. SYNCWSMARKED has no effect when
223 * loads/stores can use XKPHYS addresses with
226 /* R/W If set (and UX set), user-level loads/stores
230 * loads/stores can use XKPHYS addresses with
233 /* R/W If set (and UX set), user-level loads/stores
236 /* R/W If set, all stores act as SYNCW (NOMERGE must
239 /* R/W If set, no stores merge, and all stores reach
266 /* R/W If set, CVMSEG is available for loads/stores in
269 /* R/W If set, CVMSEG is available for loads/stores in
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| /Linux-v5.15/tools/arch/powerpc/include/asm/ |
| D | barrier.h | 15 * providing an ordering (separately) for (a) cacheable stores and (b)
16 * loads and stores to non-cacheable memory (e.g. I/O devices).
18 * mb() prevents loads and stores being reordered across this point.
20 * wmb() prevents stores being reordered across this point.
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| /Linux-v5.15/arch/sparc/kernel/ |
| D | dtlb_prot.S | 12 * [TL == 0] 1) User stores to readonly pages.
13 * [TL == 0] 2) Nucleus stores to user readonly pages.
14 * [TL > 0] 3) Nucleus stores to user readonly stack frame.
20 membar #Sync ! Synchronize stores
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| /Linux-v5.15/tools/perf/util/ |
| D | mem-events.h | 61 u32 store; /* count of all stores in trace */
62 u32 st_uncache; /* stores to uncacheable address */
64 u32 st_l1hit; /* count of stores that hit L1D */
65 u32 st_l1miss; /* count of stores that miss L1D */
85 u32 nomap; /* count of load/stores with no phys addrs */
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| /Linux-v5.15/tools/arch/ia64/include/asm/ |
| D | barrier.h | 25 * wmb(): Guarantees that all preceding stores to memory-
27 * stores and that all following stores will be
28 * visible only after all previous stores.
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| /Linux-v5.15/arch/sparc/lib/ |
| D | M7memset.S | 32 * For small 6 or fewer bytes stores, bytes will be stored.
34 * For less than 32 bytes stores, align the address on 4 byte boundary.
41 * Using BIS stores, set the first long word of each
46 * Using BIS stores, set the first long word of each of
66 * similar to prefetching for normal stores.
71 * BIS stores must be followed by a membar #StoreStore. The benefit of
79 * store and the final stores.
167 ! Use long word stores.
179 and %o2, 63, %o3 ! %o3 = bytes left after blk stores.
187 ! initial cache-clearing stores
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| /Linux-v5.15/tools/include/linux/ |
| D | refcount.h | 25 * future stores against the inc, this ensures we'll never modify the object
29 * stores will be issued before, it also provides a control dependency, which
33 * succeeded. This means the stores aren't fully ordered, but this is fine
73 * and thereby orders future stores. See the comment on top.
116 * Provides release memory ordering, such that prior loads and stores are done
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| /Linux-v5.15/include/linux/ |
| D | refcount.h | 73 * future stores against the inc, this ensures we'll never modify the object
77 * stores will be issued before, it also provides a control dependency, which
81 * succeeded. This means the stores aren't fully ordered, but this is fine
177 * and thereby orders future stores. See the comment on top.
213 * and thereby orders future stores. See the comment on top.
239 * and thereby orders future stores. See the comment on top.
297 * Provides release memory ordering, such that prior loads and stores are done
325 * Provides release memory ordering, such that prior loads and stores are done
354 * Provides release memory ordering, such that prior loads and stores are done
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| /Linux-v5.15/include/uapi/sound/ |
| D | snd_sst_tokens.h | 44 * %SKL_TKN_U8_CORE_ID: Stores module affinity value.Can take
75 * %SKL_TKN_U16_PIN_INST_ID: Stores the pin instance id
77 * %SKL_TKN_U16_MOD_INST_ID: Stores the mdule instance id
83 * %SKL_TKN_U32_OBS: Stores Output Buffer size
85 * %SKL_TKN_U32_IBS: Stores input buffer size
94 * %SKL_TKN_U32_PIPE_ID: Stores the pipe id
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| /Linux-v5.15/arch/mips/include/asm/ |
| D | sync.h | 33 * loads or stores. By way of example, if we only care that stores older
34 * than a barrier are observed prior to stores that are younger than a
36 * ordering barrier can be used. Limiting the barrier's effects to stores
38 * make progress faster than if younger loads had to wait for older stores
79 * stores, but instead causes synchronization of an icache or TLB global
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| /Linux-v5.15/fs/romfs/ |
| D | Kconfig | 20 # Select the backing stores to be supported
23 prompt "RomFS backing stores"
27 Select the backing stores to be supported.
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| /Linux-v5.15/tools/perf/pmu-events/arch/powerpc/power10/ |
| D | translation.json | 35 …efDescription": "Stores completed from S2Q (2nd-level store queue). This event includes regular st…
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| /Linux-v5.15/drivers/net/wwan/iosm/ |
| D | iosm_ipc_pm.c | 76 /* Complete all memory stores before setting bit */ in ipc_pm_wait_for_device_active()
84 /* Complete all memory stores after setting bit */ in ipc_pm_wait_for_device_active()
99 /* Complete all memory stores before clearing bit */ in ipc_pm_wait_for_device_active()
107 /* Complete all memory stores after clearing bit */ in ipc_pm_wait_for_device_active()
319 /* Complete all memory stores before clearing bit */ in ipc_pm_init()
324 /* Complete all memory stores after clearing bit */ in ipc_pm_init()
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| /Linux-v5.15/tools/perf/arch/x86/util/ |
| D | mem-events.c | 17 E("ldlat-stores", "%s/mem-stores/P", "%s/events/mem-stores"),
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| /Linux-v5.15/arch/ia64/lib/ |
| D | memset.S | 141 add ptr2 = 8, ptr1 // start of stores (beyond prefetch stores)
150 stf8 [ptr9] = fvalue, 128 // Do stores one cache line apart
155 add ptr0 = 16, ptr2 // Two stores in parallel
211 add ptr2 = 16, ptr1 // start of stores (beyond prefetch stores)
220 stf.spill [ptr9] = f0, 128 // Do stores one cache line apart
225 add ptr0 = 16, ptr2 // Two stores in parallel
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| /Linux-v5.15/sound/soc/sof/imx/ |
| D | imx-common.c | 18 * @xoops: Stores information about registers.
19 * @panic_info: Stores information about filename and line number.
20 * @stack: Stores the stack dump.
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| /Linux-v5.15/tools/perf/pmu-events/arch/x86/amdzen1/ |
| D | memory.json | 11 …n": "Counts the number of operations dispatched to the LS unit. Unit Masks ADDed. Load-op-Stores.",
17 "BriefDescription": "Counts the number of stores dispatched to the LS unit. Unit Masks ADDed.",
43 "EventName": "ls_mab_alloc.stores",
45 "BriefDescription": "LS MAB allocates by type - stores.",
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| /Linux-v5.15/fs/fscache/ |
| D | page.c | 24 val = radix_tree_lookup(&cookie->stores, page->index); in __fscache_check_page_write()
75 val = radix_tree_lookup(&cookie->stores, page->index); in __fscache_maybe_release_page()
85 if (radix_tree_tag_get(&cookie->stores, page->index, in __fscache_maybe_release_page()
96 if (radix_tree_tag_get(&cookie->stores, page->index, in __fscache_maybe_release_page()
104 xpage = radix_tree_delete(&cookie->stores, page->index); in __fscache_maybe_release_page()
158 radix_tree_tag_clear(&cookie->stores, page->index, in fscache_end_page_write()
161 if (!radix_tree_tag_get(&cookie->stores, page->index, in fscache_end_page_write()
164 xpage = radix_tree_delete(&cookie->stores, page->index); in fscache_end_page_write()
168 val = radix_tree_lookup(&cookie->stores, page->index); in fscache_end_page_write()
832 n = radix_tree_gang_lookup_tag(&cookie->stores, results, 0, 1, in fscache_write_op()
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