Searched +full:starfive +full:- +full:jh7100 +full:- +full:audio (Results 1 – 7 of 7) sorted by relevance
| /Linux-v6.1/Documentation/devicetree/bindings/clock/ |
| D | starfive,jh7100-audclk.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/clock/starfive,jh7100-audclk.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: StarFive JH7100 Audio Clock Generator
10 - Emil Renner Berthing <kernel@esmil.dk>
14 const: starfive,jh7100-audclk
21 - description: Audio source clock
22 - description: External 12.288MHz clock
23 - description: Domain 7 AHB bus clock
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| /Linux-v6.1/drivers/clk/starfive/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
4 bool "StarFive JH7100 clock support"
8 Say yes here to support the clock controller on the StarFive JH7100
12 tristate "StarFive JH7100 audio clock support"
16 Say Y or M here to support the audio clocks on the StarFive JH7100
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| D | clk-starfive-jh7100-audio.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * StarFive JH7100 Audio Clock Driver
9 #include <linux/clk-provider.h>
17 #include <dt-bindings/clock/starfive-jh7100-audio.h>
19 #include "clk-starfive-jh7100.h"
91 unsigned int idx = clkspec->args[0]; in jh7100_audclk_get()
94 return &priv->reg[idx].hw; in jh7100_audclk_get()
96 return ERR_PTR(-EINVAL); in jh7100_audclk_get()
105 priv = devm_kzalloc(&pdev->dev, struct_size(priv, reg, JH7100_AUDCLK_END), GFP_KERNEL); in jh7100_audclk_probe()
107 return -ENOMEM; in jh7100_audclk_probe()
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| D | Makefile | 1 # SPDX-License-Identifier: GPL-2.0
2 # StarFive Clock
3 obj-$(CONFIG_CLK_STARFIVE_JH7100) += clk-starfive-jh7100.o
4 obj-$(CONFIG_CLK_STARFIVE_JH7100_AUDIO) += clk-starfive-jh7100-audio.o
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| /Linux-v6.1/drivers/reset/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
12 via GPIOs or SoC-internal reset controller modules.
101 Support for the Canaan Kendryte K210 RISC-V SoC reset controller.
133 tristate "Meson Audio Memory Arbiter Reset Driver"
136 This enables the reset driver for Audio Memory Arbiter of
178 Display, GPU, Debug, AOP, Sensors, Audio, SP and APPS.
185 Raspberry Pi 4's co-processor controls some of the board's HW
188 interfacing with RPi4's co-processor and model these firmware
219 - Altera SoCFPGAs
220 - ASPEED BMC SoCs
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| D | Makefile | 1 # SPDX-License-Identifier: GPL-2.0
2 obj-y += core.o
3 obj-y += hisilicon/
4 obj-$(CONFIG_ARCH_STI) += sti/
5 obj-$(CONFIG_ARCH_TEGRA) += tegra/
6 obj-$(CONFIG_RESET_A10SR) += reset-a10sr.o
7 obj-$(CONFIG_RESET_ATH79) += reset-ath79.o
8 obj-$(CONFIG_RESET_AXS10X) += reset-axs10x.o
9 obj-$(CONFIG_RESET_BCM6345) += reset-bcm6345.o
10 obj-$(CONFIG_RESET_BERLIN) += reset-berlin.o
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| /Linux-v6.1/ |
| D | MAINTAINERS | 9 -------------------------
30 ``diff -u`` to make the patch easy to merge. Be prepared to get your
40 See Documentation/process/coding-style.rst for guidance here.
46 See Documentation/process/submitting-patches.rst for details.
57 include a Signed-off-by: line. The current version of this
59 Documentation/process/submitting-patches.rst.
70 that the bug would present a short-term risk to other users if it
76 Documentation/admin-guide/security-bugs.rst for details.
81 ---------------------------------------------------
97 W: *Web-page* with status/info
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