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/Linux-v5.4/drivers/thermal/qcom/
Dqcom-spmi-temp-alarm.c48 #define TEMP_STAGE_STEP 20000 /* Stage step: 20.000 C */
57 /* Stage 2 Threshold Min: 125 C */
59 /* Stage 2 Threshold Max: 140 C */
62 /* Temperature in Milli Celsius reported during stage 0 if no ADC is present */
72 unsigned int stage; member
75 /* protects .thresh, .stage and chip registers */
82 /* This array maps from GEN2 alarm state to GEN1 alarm stage */
104 * qpnp_tm_get_temp_stage() - return over-temperature stage
107 * Return: stage (GEN1) or state (GEN2) on success, or errno on failure.
128 * current thermal stage and threshold as well as the previous stage
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/Linux-v5.4/drivers/watchdog/
Dkempld_wdt.c10 * First the pretimeout stage runs out before the timeout stage gets
77 struct kempld_wdt_stage stage[KEMPLD_WDT_MAX_STAGES]; member
105 struct kempld_wdt_stage *stage, in kempld_wdt_set_stage_action() argument
111 if (!stage || !stage->mask) in kempld_wdt_set_stage_action()
115 stage_cfg = kempld_read8(pld, KEMPLD_WDT_STAGE_CFG(stage->id)); in kempld_wdt_set_stage_action()
124 kempld_write8(pld, KEMPLD_WDT_STAGE_CFG(stage->id), stage_cfg); in kempld_wdt_set_stage_action()
131 struct kempld_wdt_stage *stage, in kempld_wdt_set_stage_timeout() argument
143 if (!stage) in kempld_wdt_set_stage_timeout()
151 if (stage_timeout64 > stage->mask) in kempld_wdt_set_stage_timeout()
154 stage_timeout = stage_timeout64 & stage->mask; in kempld_wdt_set_stage_timeout()
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Dsbsa_gwdt.c11 * ARM SBSA Generic Watchdog has two stage timeouts:
17 * This driver can operate ARM SBSA Generic Watchdog as a single stage watchdog
19 * In the single stage mode, when the timeout is reached, your system
24 * second stage (as long as the first stage) will be reached, system will be
33 * if action is 0 (the single stage mode):
37 * Note: Since this watchdog timer has two stages, and each stage is determined
38 * by WOR, in the single stage mode, the timeout is (WOR * 2); in the two
40 * is half of that in the single stage mode.
130 * In the single stage mode, The first signal (WS0) is ignored, in sbsa_gwdt_set_timeout()
146 * In the single stage mode, if WS0 is deasserted in sbsa_gwdt_get_timeleft()
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/Linux-v5.4/drivers/gpu/drm/msm/disp/dpu1/
Ddpu_hw_lm.c16 /* These register are offset to mixer base + stage base */
50 * for the stage to be setup
52 * @stage: stage index to setup
54 static inline int _stage_offset(struct dpu_hw_mixer *ctx, enum dpu_stage stage) in _stage_offset() argument
57 if (stage != DPU_STAGE_BASE && stage <= sblk->maxblendstages) in _stage_offset()
58 return sblk->blendstage_base[stage - DPU_STAGE_0]; in _stage_offset()
100 u32 stage, u32 fg_alpha, u32 bg_alpha, u32 blend_op) in dpu_hw_lm_setup_blend_config_sdm845() argument
106 if (stage == DPU_STAGE_BASE) in dpu_hw_lm_setup_blend_config_sdm845()
109 stage_off = _stage_offset(ctx, stage); in dpu_hw_lm_setup_blend_config_sdm845()
119 u32 stage, u32 fg_alpha, u32 bg_alpha, u32 blend_op) in dpu_hw_lm_setup_blend_config() argument
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Ddpu_crtc.c81 lm->ops.setup_blend_config(lm, pstate->stage, in _dpu_crtc_setup_blend_cfg()
142 DPU_DEBUG("crtc %d stage:%d - plane %d sspp %d fb %d\n", in _dpu_crtc_blend_setup_mixer()
144 pstate->stage, in _dpu_crtc_blend_setup_mixer()
151 if (pstate->stage == DPU_STAGE_BASE && format->alpha_enable) in _dpu_crtc_blend_setup_mixer()
154 stage_idx = zpos_cnt[pstate->stage]++; in _dpu_crtc_blend_setup_mixer()
155 stage_cfg->stage[pstate->stage][stage_idx] = in _dpu_crtc_blend_setup_mixer()
157 stage_cfg->multirect_index[pstate->stage][stage_idx] = in _dpu_crtc_blend_setup_mixer()
177 1 << pstate->stage; in _dpu_crtc_blend_setup_mixer()
211 /* initialize stage cfg */ in _dpu_crtc_blend_setup()
225 /* stage config flush mask */ in _dpu_crtc_blend_setup()
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/Linux-v5.4/tools/perf/pmu-events/arch/arm64/ampere/emag/
Dcache.json156 "PublicDescription": "Level 1 stage 2 TLB refill",
159 "BriefDescription": "L1 stage 2 TLB refill"
162 "PublicDescription": "Page walk cache level-0 stage-1 hit",
165 "BriefDescription": "Page walk, L0 stage-1 hit"
168 "PublicDescription": "Page walk cache level-1 stage-1 hit",
171 "BriefDescription": "Page walk, L1 stage-1 hit"
174 "PublicDescription": "Page walk cache level-2 stage-1 hit",
177 "BriefDescription": "Page walk, L2 stage-1 hit"
180 "PublicDescription": "Page walk cache level-1 stage-2 hit",
183 "BriefDescription": "Page walk, L1 stage-2 hit"
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/Linux-v5.4/Documentation/ABI/testing/
Dsysfs-class-led-driver-sc27xx11 for the high stage. To be compatible with the hardware pattern
12 format, we should set brightness as 0 for rise stage, fall
13 stage and low stage.
15 Min stage duration: 125 ms
16 Max stage duration: 31875 ms
18 Since the stage duration step is 125 ms, the duration should be
Dsysfs-bus-iio-health-afe440x7 specific stage number corresponding to datasheet stage names
15 calculated difference in the value of stage 1 - 2 and 3 - 4.
33 Transimpedance Amplifier during the associated stage.
41 this stage. Y is the specific stage number.
/Linux-v5.4/tools/testing/selftests/tc-testing/
DTdcPlugin.py43 def adjust_command(self, stage, command): argument
46 print(' -- {}.adjust_command {}'.format(self.sub_class, stage))
48 # if stage == 'pre':
50 # elif stage == 'setup':
52 # elif stage == 'execute':
54 # elif stage == 'verify':
56 # elif stage == 'teardown':
58 # elif stage == 'post':
Dtdc.py33 def __init__(self, stage, output, message): argument
34 self.stage = stage
157 def call_adjust_command(self, stage, command): argument
159 command = pgn_inst.adjust_command(stage, command)
180 def exec_cmd(args, pm, stage, command): argument
190 command = pm.call_adjust_command(stage, command)
214 def prepare_env(args, pm, stage, prefix, cmdlist, output = None): argument
232 (proc, foutput) = exec_cmd(args, pm, stage, cmd)
246 stage, output,
272 prepare_env(args, pm, 'setup', "-----> prepare stage", tidx["setup"])
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DREADME87 stage does some setup if the test needs it. The teardown stage undoes
92 The execute and verify stages each run one command. The execute stage
94 verify stage checks the return code for success, and also compares
97 Each of the commands in any stage will run in a shell instance.
134 -P, --pause Pause execution just before post-suite stage
200 pre- and post-execute stage
201 adjust-command (runs in all stages and receives the stage name)
205 failure during setup or teardown stage.
209 The adjust-command hook receives the stage id (see list below) and the
236 runs each command in the execute stage under valgrind,
/Linux-v5.4/tools/testing/selftests/kvm/x86_64/
Dsmm_test.c41 * SMI handler always report back fixed stage SMRAM_STAGE.
96 int stage, stage_reported; in main() local
124 for (stage = 1;; stage++) { in main()
127 "Stage %d: unexpected exit reason: %u (%s),\n", in main()
128 stage, run->exit_reason, in main()
139 TEST_ASSERT(stage_reported == stage || in main()
141 "Unexpected stage: #%x, got %x", in main()
142 stage, stage_reported); in main()
Devmcs_test.c81 int stage; in main() local
103 for (stage = 1;; stage++) { in main()
106 "Stage %d: unexpected exit reason: %u (%s),\n", in main()
107 stage, run->exit_reason, in main()
125 uc.args[1] == stage, "Unexpected register values vmexit #%lx, got %lx", in main()
126 stage, (ulong)uc.args[1]); in main()
Dstate_test.c129 int stage; in main() local
146 for (stage = 1;; stage++) { in main()
149 "Stage %d: unexpected exit reason: %u (%s),\n", in main()
150 stage, run->exit_reason, in main()
168 uc.args[1] == stage, "Unexpected register values vmexit #%lx, got %lx", in main()
169 stage, (ulong)uc.args[1]); in main()
/Linux-v5.4/tools/testing/selftests/tc-testing/plugin-lib/
DnsPlugin.py45 def adjust_command(self, stage, command): argument
46 super().adjust_command(stage, command)
61 if stage == 'setup' or stage == 'execute' or stage == 'verify' or stage == 'teardown':
63 …print('adjust_command: stage is {}; inserting netns stuff in command [{}] list [{}]'.format(stage…
121 def _exec_cmd(self, stage, command): argument
129 self.adjust_command(stage, command)
/Linux-v5.4/sound/soc/sprd/
Dsprd-pcm-compress.c28 /* Stage 0 IRAM buffer size definition */
36 /* Stage 1 DDR buffer size definition */
52 * The Spreadtrum Audio compress offload mode will use 2-stage DMA transfer to
58 * For 2-stage DMA transfer, we can allocate 2 buffers: IRAM buffer (always
77 /* Stage 0 IRAM buffer */
79 /* Stage 1 DDR buffer */
91 /* Stage 0 IRAM buffer received data size */
93 /* Stage 1 DDR buffer received data size */
95 /* Stage 1 DDR buffer pointer */
277 * Configure the DMA engine 2-stage transfer mode. Channel 1 set as the in sprd_platform_compr_set_params()
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/Linux-v5.4/drivers/gpu/drm/msm/disp/mdp5/
Dmdp5_ctl.c287 enum mdp_mixer_stage_id stage) in mdp_ctl_blend_mask() argument
290 case SSPP_VIG0: return MDP5_CTL_LAYER_REG_VIG0(stage); in mdp_ctl_blend_mask()
291 case SSPP_VIG1: return MDP5_CTL_LAYER_REG_VIG1(stage); in mdp_ctl_blend_mask()
292 case SSPP_VIG2: return MDP5_CTL_LAYER_REG_VIG2(stage); in mdp_ctl_blend_mask()
293 case SSPP_RGB0: return MDP5_CTL_LAYER_REG_RGB0(stage); in mdp_ctl_blend_mask()
294 case SSPP_RGB1: return MDP5_CTL_LAYER_REG_RGB1(stage); in mdp_ctl_blend_mask()
295 case SSPP_RGB2: return MDP5_CTL_LAYER_REG_RGB2(stage); in mdp_ctl_blend_mask()
296 case SSPP_DMA0: return MDP5_CTL_LAYER_REG_DMA0(stage); in mdp_ctl_blend_mask()
297 case SSPP_DMA1: return MDP5_CTL_LAYER_REG_DMA1(stage); in mdp_ctl_blend_mask()
298 case SSPP_VIG3: return MDP5_CTL_LAYER_REG_VIG3(stage); in mdp_ctl_blend_mask()
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Dmdp5_ctl.h46 * @stage: array to contain the pipe num for each stage
47 * @stage_cnt: valid stage number in stage array
56 enum mdp5_pipe stage[][MAX_PIPE_STAGE],
Dmdp5_crtc.c182 static inline u32 mdp5_lm_use_fg_alpha_mask(enum mdp_mixer_stage_id stage) in mdp5_lm_use_fg_alpha_mask() argument
184 switch (stage) { in mdp5_lm_use_fg_alpha_mask()
198 * left/right pipe offsets for the stage array used in blend_setup()
207 * Otherwise all layers will be blended based on their stage calculated
227 enum mdp5_pipe stage[STAGE_MAX + 1][MAX_PIPE_STAGE] = { { SSPP_NONE } }; in blend_setup() enum
233 #define blender(stage) ((stage) - STAGE0) in blend_setup() argument
252 pstates[pstate->stage] = pstate; in blend_setup()
253 stage[pstate->stage][PIPE_LEFT] = mdp5_plane_pipe(plane); in blend_setup()
255 * if we have a right mixer, stage the same pipe as we in blend_setup()
259 r_stage[pstate->stage][PIPE_LEFT] = in blend_setup()
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/Linux-v5.4/drivers/net/wireless/broadcom/b43/
Dphy_n.h340 #define B43_NPHY_TXF_20CO_AS0 B43_PHY_N(0x0CC) /* TX filter 20 coeff A stage 0 */
341 #define B43_NPHY_TXF_20CO_AS1 B43_PHY_N(0x0CD) /* TX filter 20 coeff A stage 1 */
342 #define B43_NPHY_TXF_20CO_AS2 B43_PHY_N(0x0CE) /* TX filter 20 coeff A stage 2 */
343 #define B43_NPHY_TXF_20CO_B32S0 B43_PHY_N(0x0CF) /* TX filter 20 coeff B32 stage 0 */
344 #define B43_NPHY_TXF_20CO_B1S0 B43_PHY_N(0x0D0) /* TX filter 20 coeff B1 stage 0 */
345 #define B43_NPHY_TXF_20CO_B32S1 B43_PHY_N(0x0D1) /* TX filter 20 coeff B32 stage 1 */
346 #define B43_NPHY_TXF_20CO_B1S1 B43_PHY_N(0x0D2) /* TX filter 20 coeff B1 stage 1 */
347 #define B43_NPHY_TXF_20CO_B32S2 B43_PHY_N(0x0D3) /* TX filter 20 coeff B32 stage 2 */
348 #define B43_NPHY_TXF_20CO_B1S2 B43_PHY_N(0x0D4) /* TX filter 20 coeff B1 stage 2 */
364 #define B43_NPHY_TXF_40CO_AS0 B43_PHY_N(0x0E1) /* TX filter 40 coeff A stage 0 */
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/Linux-v5.4/drivers/gpu/drm/msm/disp/mdp4/
Dmdp4_kms.h102 enum mdp4_pipe pipe, enum mdp_mixer_stage_id stage) in mixercfg() argument
108 mixer_cfg |= MDP4_LAYERMIXER_IN_CFG_PIPE0(stage) | in mixercfg()
114 mixer_cfg |= MDP4_LAYERMIXER_IN_CFG_PIPE1(stage) | in mixercfg()
120 mixer_cfg |= MDP4_LAYERMIXER_IN_CFG_PIPE2(stage) | in mixercfg()
126 mixer_cfg |= MDP4_LAYERMIXER_IN_CFG_PIPE3(stage) | in mixercfg()
132 mixer_cfg |= MDP4_LAYERMIXER_IN_CFG_PIPE4(stage) | in mixercfg()
138 mixer_cfg |= MDP4_LAYERMIXER_IN_CFG_PIPE5(stage) | in mixercfg()
144 mixer_cfg |= MDP4_LAYERMIXER_IN_CFG_PIPE6(stage) | in mixercfg()
/Linux-v5.4/tools/testing/selftests/tc-testing/creating-plugins/
DAddingPlugins.txt18 pre (the pre-suite stage)
23 post (the post-suite stage)
36 def adjust_command(self, stage, command) # see "ADJUST" below
71 the execution stage and a string which is the actual command to be
72 executed. The plugin can adjust the command, based on the stage of
/Linux-v5.4/drivers/usb/gadget/udc/
Dgr_udc.h179 GR_EP0_IDATA, /* IN data stage */
180 GR_EP0_ODATA, /* OUT data stage */
181 GR_EP0_ISTATUS, /* Status stage after IN data stage */
182 GR_EP0_OSTATUS, /* Status stage after OUT data stage */
/Linux-v5.4/drivers/usb/renesas_usbhs/
Dcommon.h142 #define CTRE (1 << 11) /* Enable IRQ Control Stage Transition */
158 #define CTRT (1 << 11) /* Control Stage Interrupt Status */
170 #define CTSQ_MASK (0x7) /* Control Transfer Stage */
171 #define IDLE_SETUP_STAGE 0 /* Idle stage or setup stage */
172 #define READ_DATA_STAGE 1 /* Control read data stage */
173 #define READ_STATUS_STAGE 2 /* Control read status stage */
174 #define WRITE_DATA_STAGE 3 /* Control write data stage */
175 #define WRITE_STATUS_STAGE 4 /* Control write status stage */
176 #define NODATA_STATUS_STAGE 5 /* Control write NoData status stage */
/Linux-v5.4/drivers/media/radio/wl128x/
Dfmdrv_common.c170 fmdev->irq_info.handlers[fmdev->irq_info.stage](fmdev); in fm_irq_call()
174 static inline void fm_irq_call_stage(struct fmdev *fmdev, u8 stage) in fm_irq_call_stage() argument
176 fmdev->irq_info.stage = stage; in fm_irq_call_stage()
180 static inline void fm_irq_timeout_stage(struct fmdev *fmdev, u8 stage) in fm_irq_timeout_stage() argument
182 fmdev->irq_info.stage = stage; in fm_irq_timeout_stage()
276 if (irq_info->stage != 0) { in recv_tasklet()
277 fmerr("Inval stage resetting to zero\n"); in recv_tasklet()
278 irq_info->stage = 0; in recv_tasklet()
285 irq_info->handlers[irq_info->stage](fmdev); in recv_tasklet()
312 irq_info->handlers[irq_info->stage](fmdev); in recv_tasklet()
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