Searched +full:stacked +full:- +full:memories (Results 1 – 4 of 4) sorted by relevance
| /Linux-v6.6/Documentation/devicetree/bindings/spi/ |
| D | spi-peripheral-props.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-peripheral-props.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Peripheral-specific properties for a SPI bus.
11 be common properties like spi-max-frequency, spi-cpha, etc. or they could be
13 need to be defined in the peripheral node because they are per-peripheral and
19 - Mark Brown <broonie@kernel.org>
27 - minimum: 0
32 spi-cs-high:
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| D | spi-controller.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mark Brown <broonie@kernel.org>
20 pattern: "^spi(@.*|-([0-9]|[1-9][0-9]+))?$"
22 "#address-cells":
25 "#size-cells":
28 cs-gpios:
32 increased automatically with max(cs-gpios, hardware chip selects).
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| /Linux-v6.6/drivers/mtd/lpddr/ |
| D | lpddr2_nvm.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * LPDDR2-NVM MTD driver. This module provides read, write, erase, lock/unlock
4 * support for LPDDR2-NVM PCM memories
54 /* LPDDR2-NVM Commands */
63 /* LPDDR2-NVM Registers offset */
72 * &bus_width: memory bus-width (eg: x16 2 Bytes, x32 4 Bytes)
92 * Build Mode Register Configuration DataMask based on device bus-width
105 * Build Status Register OK DataMask based on device bus-width
123 struct pcm_int_data *pcm_data = map->fldrv_priv; in ow_reg_add()
125 val = map->pfow_base + offset*pcm_data->bus_width; in ow_reg_add()
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| /Linux-v6.6/Documentation/driver-api/ |
| D | edac.rst | 5 ----------------------------------------
8 *sockets, *socket sets*, *banks*, *rows*, *chip-select rows*, *channels*,
43 It is typically the highest hierarchy on a Fully-Buffered DIMM memory
52 * Single-channel
55 only. E. g. if the data is 64 bits-wide, the data flows to the CPU using
57 memories. FB-DIMM and RAMBUS use a different concept for channel, so
60 * Double-channel
63 dimms, accessed at the same time. E. g. if the DIMM is 64 bits-wide (72
67 * Chip-select row
70 accessed. Common chip-select rows for single channel are 64 bits, for
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