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/Linux-v6.6/arch/arm64/boot/dts/mediatek/
Dmt8365-evk.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2021-2022 BayLibre, SAS.
9 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/input.h>
13 #include <dt-bindings/pinctrl/mt8365-pinfunc.h>
19 compatible = "mediatek,mt8365-evk", "mediatek,mt8365";
26 stdout-path = "serial0:921600n8";
31 compatible = "linaro,optee-tz";
36 gpio-keys {
[all …]
Dmt7622-rfb1.dts6 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
9 /dts-v1/;
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/gpio/gpio.h>
18 chassis-type = "embedded";
19 compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622";
26 stdout-path = "serial0:115200n8";
32 proc-supply = <&mt6380_vcpu_reg>;
33 sram-supply = <&mt6380_vm_reg>;
37 proc-supply = <&mt6380_vcpu_reg>;
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Dmt8173-evb.dts1 // SPDX-License-Identifier: GPL-2.0-only
7 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
13 chassis-type = "embedded";
14 compatible = "mediatek,mt8173-evb", "mediatek,mt8173";
31 compatible = "hdmi-connector";
37 remote-endpoint = <&hdmi0_out>;
43 compatible = "linux,extcon-usb-gpio";
44 id-gpio = <&pio 16 GPIO_ACTIVE_HIGH>;
48 compatible = "regulator-fixed";
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Dmt7622-bananapi-bpi-r64.dts5 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 /dts-v1/;
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/leds/common.h>
17 model = "Bananapi BPI-R64";
18 chassis-type = "embedded";
19 compatible = "bananapi,bpi-r64", "mediatek,mt7622";
26 stdout-path = "serial0:115200n8";
32 proc-supply = <&mt6380_vcpu_reg>;
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Dmt8195-cherry.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/spmi/spmi.h>
25 backlight_lcd0: backlight-lcd0 {
26 compatible = "pwm-backlight";
27 brightness-levels = <0 1023>;
28 default-brightness-level = <576>;
29 enable-gpios = <&pio 82 GPIO_ACTIVE_HIGH>;
30 num-interpolated-steps = <1023>;
32 power-supply = <&ppvar_sys>;
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Dmt8173-elm.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <dt-bindings/input/input.h>
7 #include <dt-bindings/input/linux-event-codes.h>
8 #include <dt-bindings/regulator/dlg,da9211-regulator.h>
9 #include <dt-bindings/gpio/gpio.h>
25 compatible = "pwm-backlight";
27 power-supply = <&bl_fixed_reg>;
28 enable-gpios = <&pio 95 GPIO_ACTIVE_HIGH>;
30 pinctrl-names = "default";
31 pinctrl-0 = <&panel_backlight_en_pins>;
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/Linux-v6.6/Documentation/devicetree/bindings/cpufreq/
Dcpufreq-mediatek.txt5 - clocks: A list of phandle + clock-specifier pairs for the clocks listed in clock names.
6 - clock-names: Should contain the following:
7 "cpu" - The multiplexer for clock input of CPU cluster.
8 "intermediate" - A parent of "cpu" clock which is used as "intermediate" clock
11 Please refer to Documentation/devicetree/bindings/clock/clock-bindings.txt for
13 - operating-points-v2: Please refer to Documentation/devicetree/bindings/opp/opp-v2.yaml
15 - proc-supply: Regulator for Vproc of CPU cluster.
18 - sram-supply: Regulator for Vsram of CPU cluster. When present, the cpufreq driver
23 - mediatek,cci:
30 - #cooling-cells:
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/Linux-v6.6/Documentation/devicetree/bindings/gpu/
Darm,mali-bifrost.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/gpu/arm,mali-bifrost.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <robh@kernel.org>
14 pattern: '^gpu@[a-f0-9]+$'
18 - items:
19 - enum:
20 - amlogic,meson-g12a-mali
21 - mediatek,mt8183-mali
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/Linux-v6.6/Documentation/devicetree/bindings/interconnect/
Dmediatek,cci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jia-Wei Chang <jia-wei.chang@mediatek.com>
11 - Johnson Wang <johnson.wang@mediatek.com>
21 - mediatek,mt8183-cci
22 - mediatek,mt8186-cci
26 - description:
28 - description:
33 clock-names:
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/Linux-v6.6/drivers/soc/mediatek/
Dmtk-regulator-coupler.c1 // SPDX-License-Identifier: GPL-2.0-only
30 * This function is limited to the GPU<->SRAM voltages relationships.
37 int max_spread = rdev->constraints->max_spread[0]; in mediatek_regulator_balance_voltage()
38 int vsram_min_uV = mrc->vsram_rdev->constraints->min_uV; in mediatek_regulator_balance_voltage()
39 int vsram_max_uV = mrc->vsram_rdev->constraints->max_uV; in mediatek_regulator_balance_voltage()
46 * If the target device is on, setting the SRAM voltage directly in mediatek_regulator_balance_voltage()
47 * is not supported as it scales through its coupled supply voltage. in mediatek_regulator_balance_voltage()
50 * that this is the first time we power up the SRAM regulator, which in mediatek_regulator_balance_voltage()
54 if (rdev == mrc->vsram_rdev) { in mediatek_regulator_balance_voltage()
55 if (rdev->use_count == 0) in mediatek_regulator_balance_voltage()
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/Linux-v6.6/arch/arm/boot/dts/st/
Dste-dbx5x0.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include <dt-bindings/interrupt-controller/irq.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/clock/ste-db8500-clkout.h>
9 #include <dt-bindings/reset/stericsson,db8500-prcc-reset.h>
10 #include <dt-bindings/mfd/dbx500-prcmu.h>
11 #include <dt-bindings/arm/ux500_pm_domains.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/thermal/thermal.h>
16 #address-cells = <1>;
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/Linux-v6.6/arch/arm/boot/dts/samsung/
Dexynos4210-universal_c210.dts1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2012-2013 Samsung Electronics Co., Ltd.
12 /dts-v1/;
14 #include <dt-bindings/gpio/gpio.h>
19 chassis-type = "handset";
35 stdout-path = "serial2:115200n8";
39 fixed-rate-clocks {
41 compatible = "samsung,clock-xxti";
42 clock-frequency = <0>;
46 compatible = "samsung,clock-xusbxti";
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/Linux-v6.6/arch/arm/boot/dts/nspire/
Dnspire.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
7 #address-cells = <1>;
8 #size-cells = <1>;
9 interrupt-parent = <&intc>;
12 #address-cells = <1>;
13 #size-cells = <0>;
16 compatible = "arm,arm926ej-s";
26 sram: sram@a4000000 { label
27 compatible = "mmio-sram";
29 #address-cells = <1>;
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/Linux-v6.6/arch/arm/boot/dts/nxp/imx/
Dimx27-phytec-phycore-som.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
6 /dts-v1/;
11 compatible = "phytec,imx27-pcm038", "fsl,imx27";
18 reg_3v3: regulator-0 {
19 compatible = "regulator-fixed";
20 regulator-name = "3V3";
21 regulator-min-microvolt = <3300000>;
22 regulator-max-microvolt = <3300000>;
25 reg_5v0: regulator-1 {
26 compatible = "regulator-fixed";
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Dimx6q.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 #include <dt-bindings/interrupt-controller/irq.h>
6 #include "imx6q-pinfunc.h"
16 #address-cells = <1>;
17 #size-cells = <0>;
20 compatible = "arm,cortex-a9";
23 next-level-cache = <&L2>;
24 operating-points = <
32 fsl,soc-operating-points = <
33 /* ARM kHz SOC-PU uV */
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Dimx6dl.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 #include <dt-bindings/interrupt-controller/irq.h>
6 #include "imx6dl-pinfunc.h"
15 #address-cells = <1>;
16 #size-cells = <0>;
19 compatible = "arm,cortex-a9";
22 next-level-cache = <&L2>;
23 operating-points = <
29 fsl,soc-operating-points = <
30 /* ARM kHz SOC-PU uV */
[all …]
Dimx7d-smegw01.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
13 compatible = "storopack,imx7d-smegw01", "fsl,imx7d";
26 stdout-path = &uart1;
34 reg_lte_on: regulator-lte-on {
35 compatible = "regulator-fixed";
36 pinctrl-names = "default";
37 pinctrl-0 = <&pinctrl_lte_on>;
38 regulator-min-microvolt = <3300000>;
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/Linux-v6.6/arch/arm/boot/dts/qcom/
Dqcom-apq8064-asus-nexus7-flo.dts1 // SPDX-License-Identifier: GPL-2.0
2 #include "qcom-apq8064-v2.0.dtsi"
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/input/input.h>
5 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
8 compatible = "asus,nexus7-flo", "qcom,apq8064";
9 chassis-type = "tablet";
17 stdout-path = "serial0:115200n8";
20 reserved-memory {
21 #address-cells = <1>;
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/Linux-v6.6/arch/sparc/include/asm/
Dfhc.h1 /* SPDX-License-Identifier: GPL-2.0 */
44 #define FHC_CONTROL_DCD 0x00008000 /* DC-->DC Converter Disable */
47 #define FHC_CONTROL_AOFF 0x00001000 /* CPU A SRAM/SBD Low Power Mode */
48 #define FHC_CONTROL_BOFF 0x00000800 /* CPU B SRAM/SBD Low Power Mode */
49 #define FHC_CONTROL_PSOFF 0x00000400 /* Turns off this FHC's power supply */
/Linux-v6.6/Documentation/devicetree/bindings/power/
Drockchip-io-domain.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/power/rockchip-io-domain.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip SRAM for IO Voltage Domains
10 - Heiko Stuebner <heiko@sntech.de>
42 to report their voltage. The IO Voltage Domain for any non-specified
48 - rockchip,px30-io-voltage-domain
49 - rockchip,px30-pmu-io-voltage-domain
50 - rockchip,rk3188-io-voltage-domain
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/Linux-v6.6/drivers/net/wireless/intel/iwlegacy/
D4965.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
8 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
15 #include <linux/dma-mapping.h>
29 * il_verify_inst_sparse - verify runtime uCode image in card vs. host,
44 /* read data comes through single port, auto-incr addr */ in il4965_verify_inst_sparse()
50 ret = -EIO; in il4965_verify_inst_sparse()
61 * il4965_verify_inst_full - verify runtime uCode image in card vs. host,
77 for (; len > 0; len -= sizeof(u32), image++) { in il4965_verify_inst_full()
78 /* read data comes through single port, auto-incr addr */ in il4965_verify_inst_full()
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/Linux-v6.6/arch/arm/boot/dts/nxp/lpc/
Dlpc4350-hitex-eval.dts9 * Released under the terms of 3-clause BSD License
13 /dts-v1/;
18 #include "dt-bindings/input/input.h"
19 #include "dt-bindings/gpio/gpio.h"
23 compatible = "hitex,lpc4350-eval-board", "nxp,lpc4350";
33 stdout-path = &uart0;
42 compatible = "gpio-keys-polled";
43 poll-interval = <100>;
97 compatible = "gpio-leds";
102 linux,default-trigger = "heartbeat";
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/Linux-v6.6/drivers/pmdomain/mediatek/
Dmtk-scpsys.c1 // SPDX-License-Identifier: GPL-2.0-only
16 #include <dt-bindings/power/mt2701-power.h>
17 #include <dt-bindings/power/mt2712-power.h>
18 #include <dt-bindings/power/mt6797-power.h>
19 #include <dt-bindings/power/mt7622-power.h>
20 #include <dt-bindings/power/mt7623a-power.h>
21 #include <dt-bindings/power/mt8173-power.h>
28 #define MTK_SCPD_CAPS(_scpd, _x) ((_scpd)->data->caps & (_x))
112 * struct scp_domain_data - scp domain data for power on/off flow
116 * @sram_pdn_bits: The mask for sram power control bits.
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/Linux-v6.6/drivers/mmc/host/
Dmeson-gx-mmc.c1 // SPDX-License-Identifier: GPL-2.0-only
17 #include <linux/dma-mapping.h>
21 #include <linux/mmc/slot-gpio.h>
24 #include <linux/clk-provider.h>
31 #define DRIVER_NAME "meson-gx-mmc"
51 #define CLK_TX_DELAY_MASK(h) (h->data->tx_delay_mask)
52 #define CLK_RX_DELAY_MASK(h) (h->data->rx_delay_mask)
53 #define CLK_ALWAYS_ON(h) (h->data->always_on)
54 #define CLK_IRQ_SDIO_SLEEP(h) (h->data->irq_sdio_sleep)
207 unsigned int timeout = data->timeout_ns / NSEC_PER_MSEC; in meson_mmc_get_timeout_msecs()
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/Linux-v6.6/arch/arm/mach-rockchip/
Dpm.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Author: Tony Xie <tony.xie@rock-chips.com>
55 rkpm_bootdata_cpusp = rk3288_bootram_phy + (SZ_4K - 8); in rk3288_config_bootdata()
99 * SGRF_FAST_BOOT_EN - system to boot from FAST_BOOT_ADDR in rk3288_slp_mode_set()
100 * PCLK_WDT_GATE - disable WDT during suspend. in rk3288_slp_mode_set()
142 * switch its main clock supply to the alternative 32kHz in rk3288_slp_mode_set()
237 "rockchip,rk3288-sgrf"); in rk3288_suspend_init()
244 "rockchip,rk3288-grf"); in rk3288_suspend_init()
251 "rockchip,rk3288-pmu-sram"); in rk3288_suspend_init()
254 return -ENODEV; in rk3288_suspend_init()
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