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/Linux-v5.10/arch/arm64/boot/dts/arm/
Dfoundation-v8-spin-table.dtsi4 * ARMv8 Foundation model DTS (spin table configuration)
8 enable-method = "spin-table";
9 cpu-release-addr = <0x0 0x8000fff8>;
13 enable-method = "spin-table";
14 cpu-release-addr = <0x0 0x8000fff8>;
18 enable-method = "spin-table";
19 cpu-release-addr = <0x0 0x8000fff8>;
23 enable-method = "spin-table";
24 cpu-release-addr = <0x0 0x8000fff8>;
Drtsm_ve-aemv8a.dts1 // SPDX-License-Identifier: GPL-2.0
5 * Architecture Envelope Model (AEM) ARMv8-A
11 /dts-v1/;
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 #include "rtsm_ve-motherboard.dtsi"
22 interrupt-parent = <&gic>;
23 #address-cells = <2>;
24 #size-cells = <2>;
36 #address-cells = <2>;
37 #size-cells = <0>;
[all …]
Dfoundation-v8.dts1 // SPDX-License-Identifier: GPL-2.0
8 #include "foundation-v8.dtsi"
9 #include "foundation-v8-gicv2.dtsi"
10 #include "foundation-v8-spin-table.dtsi"
Dfoundation-v8-gicv3.dts1 // SPDX-License-Identifier: GPL-2.0
8 #include "foundation-v8.dtsi"
9 #include "foundation-v8-gicv3.dtsi"
10 #include "foundation-v8-spin-table.dtsi"
/Linux-v5.10/Documentation/devicetree/bindings/arm/
Dcpus.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
21 with updates for 32-bit and 64-bit ARM systems provided in this document.
30 - square brackets define bitfields, eg reg[7:0] value of the bitfield in
59 On 32-bit ARM v7 or later systems this property is
68 On ARM v8 64-bit systems this property is required
71 * If cpus node's #address-cells property is set to 2
79 * If cpus node's #address-cells property is set to 1
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/Linux-v5.10/drivers/gpu/drm/i915/gt/
Dselftest_mocs.c2 * SPDX-License-Identifier: MIT
30 ce->ring = __intel_context_ring_size(SZ_16K); in mocs_context_create()
40 err = -ETIME; in request_add_sync()
46 static int request_add_spin(struct i915_request *rq, struct igt_spinner *spin) in request_add_spin() argument
52 if (spin && !igt_wait_for_spinner(spin, rq)) in request_add_spin()
53 err = -ETIME; in request_add_spin()
65 obj = i915_gem_object_create_internal(gt->i915, PAGE_SIZE); in create_scratch()
71 vma = i915_vma_instance(obj, &gt->ggtt->vm, NULL); in create_scratch()
88 struct drm_i915_mocs_table table; in live_mocs_init() local
94 flags = get_mocs_settings(gt->i915, &table); in live_mocs_init()
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/Linux-v5.10/Documentation/devicetree/bindings/cpu/
Dcpu-topology.txt6 1 - Introduction
12 - socket
13 - cluster
14 - core
15 - thread
18 symmetric multi-threading (SMT) is supported or not.
29 Currently, only ARM/RISC-V intend to use this cpu topology binding but it may be
39 2 - cpu-map node
42 The ARM/RISC-V CPU topology is defined within the cpu-map node, which is a direct
46 - cpu-map node
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/Linux-v5.10/arch/arm/boot/dts/
Dbcm2837.dtsi2 #include "bcm2835-common.dtsi"
3 #include "bcm2835-rpi-common.dtsi"
11 dma-ranges = <0xc0000000 0x00000000 0x3f000000>;
14 compatible = "brcm,bcm2836-l1-intc";
16 interrupt-controller;
17 #interrupt-cells = <2>;
18 interrupt-parent = <&local_intc>;
22 arm-pmu {
23 compatible = "arm,cortex-a53-pmu";
24 interrupt-parent = <&local_intc>;
[all …]
Dbcm2711.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/soc/bcm2835-pm.h>
10 #address-cells = <2>;
11 #size-cells = <1>;
13 interrupt-parent = <&gicv2>;
16 compatible = "brcm,bcm2711-vc5";
20 clk_27MHz: clk-27M {
21 #clock-cells = <0>;
22 compatible = "fixed-clock";
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/Linux-v5.10/arch/arm64/boot/dts/toshiba/
Dtmpv7708.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * (C) Copyright 2018 - 2020, Toshiba Corporation.
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 /memreserve/ 0x81000000 0x00300000; /* cpu-release-addr */
17 #address-cells = <2>;
18 #size-cells = <2>;
21 #address-cells = <1>;
22 #size-cells = <0>;
24 cpu-map {
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/Linux-v5.10/arch/arm64/boot/dts/freescale/
Ds32v234.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2015-2016 Freescale Semiconductor, Inc.
4 * Copyright 2016-2018 NXP
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 interrupt-parent = <&gic>;
14 #address-cells = <2>;
15 #size-cells = <2>;
23 #address-cells = <2>;
24 #size-cells = <0>;
28 compatible = "arm,cortex-a53";
[all …]
/Linux-v5.10/arch/powerpc/platforms/85xx/
Dsmp.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Copyright 2006-2008, 2011-2012, 2015 Freescale Semiconductor Inc.
26 #include <asm/code-patching.h>
59 qoriq_pm_ops->freeze_time_base(true); in mpc85xx_give_timebase()
62 * e5500/e6500 have a workaround for erratum A-006958 in place in mpc85xx_give_timebase()
63 * that will reread the timebase until TBL is non-zero. in mpc85xx_give_timebase()
67 * TBL is non-zero, we ensure that TB does not change. We don't in mpc85xx_give_timebase()
92 qoriq_pm_ops->freeze_time_base(false); in mpc85xx_give_timebase()
122 qoriq_pm_ops->irq_mask(cpu); in smp_85xx_cpu_offline_self()
131 cur_cpu_spec->cpu_down_flush(); in smp_85xx_cpu_offline_self()
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/Linux-v5.10/Documentation/hwmon/
Dlm93.rst10 Addresses scanned: I2C 0x2c-0x2e
18 Addresses scanned: I2C 0x2c-0x2e
24 - Mark M. Hoffman <mhoffman@lightlink.com>
25 - Ported to 2.6 by Eric J. Bowersox <ericb@aspsys.com>
26 - Adapted to 2.6.20 by Carsten Emde <ce@osadl.org>
27 - Modified for mainline integration by Hans J. Koch <hjk@hansjkoch.de>
30 -----------------
33 Set to non-zero to force some initializations (default is 0).
38 Configures in7 and in8 limit type, where 0 means absolute and non-zero
54 --------------------
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/Linux-v5.10/arch/powerpc/boot/dts/
Diss4xx-mpic.dts15 /dts-v1/;
20 #address-cells = <2>;
21 #size-cells = <1>;
22 model = "ibm,iss-4xx";
23 compatible = "ibm,iss-4xx";
24 dcr-parent = <&{/cpus/cpu@0}>;
31 #address-cells = <1>;
32 #size-cells = <0>;
38 clock-frequency = <100000000>; // 100Mhz :-)
39 timebase-frequency = <100000000>;
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Dcurrituck.dts11 /dts-v1/;
13 /memreserve/ 0x01f00000 0x00100000; // spin table
16 #address-cells = <2>;
17 #size-cells = <2>;
20 dcr-parent = <&{/cpus/cpu@0}>;
27 #address-cells = <1>;
28 #size-cells = <0>;
34 clock-frequency = <1600000000>; // 1.6 GHz
35 timebase-frequency = <100000000>; // 100Mhz
36 i-cache-line-size = <32>;
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/Linux-v5.10/arch/arm64/kernel/
Dsmp_spin_table.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Spin Table SMP initialisation
50 return -ENODEV; in smp_spin_table_cpu_init()
55 ret = of_property_read_u64(dn, "cpu-release-addr", in smp_spin_table_cpu_init()
58 pr_err("CPU %d: missing or invalid cpu-release-addr property\n", in smp_spin_table_cpu_init()
71 return -ENODEV; in smp_spin_table_cpu_prepare()
74 * The cpu-release-addr may or may not be inside the linear mapping. in smp_spin_table_cpu_prepare()
82 return -ENOMEM; in smp_spin_table_cpu_prepare()
86 * endianness of the kernel. Therefore, any boot-loaders that in smp_spin_table_cpu_prepare()
88 * boot-loader's endianness before jumping. This is mandated by in smp_spin_table_cpu_prepare()
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Dcpu_ops.c1 // SPDX-License-Identifier: GPL-2.0-only
46 if (!strcmp(name, (*ops)->name)) in cpu_get_ops()
68 enable_method = of_get_property(dn, "enable-method", NULL); in cpu_read_enable_method()
72 * when spin-table is used for secondaries). in cpu_read_enable_method()
76 pr_err("%pOF: missing enable-method property\n", in cpu_read_enable_method()
90 pr_err("Unsupported ACPI enable-method\n"); in cpu_read_enable_method()
104 return -ENODEV; in init_cpu_ops()
108 pr_warn("Unsupported enable-method: %s\n", enable_method); in init_cpu_ops()
109 return -EOPNOTSUPP; in init_cpu_ops()
/Linux-v5.10/kernel/locking/
Dqspinlock_paravirt.h1 /* SPDX-License-Identifier: GPL-2.0 */
16 * pv_wait(u8 *ptr, u8 val) -- suspends the vcpu if *ptr == val
17 * pv_kick(cpu) -- wakes a suspended vcpu
31 * mitigates the slight slowdown for non-overcommitted guest with this
32 * aggressive wait-early mechanism.
64 * pv_wait_head_or_lock() to signal that it is ready to spin on the lock.
88 int val = atomic_read(&lock->val); in pv_hybrid_queued_unfair_trylock()
91 (cmpxchg_acquire(&lock->locked, 0, _Q_LOCKED_VAL) == 0)) { in pv_hybrid_queued_unfair_trylock()
111 WRITE_ONCE(lock->pending, 1); in set_pending()
121 return !READ_ONCE(lock->locked) && in trylock_clear_pending()
[all …]
/Linux-v5.10/arch/arm64/boot/dts/apm/
Dapm-shadowcat.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * dts file for AppliedMicro (APM) X-Gene Shadowcat SOC
9 compatible = "apm,xgene-shadowcat";
10 interrupt-parent = <&gic>;
11 #address-cells = <2>;
12 #size-cells = <2>;
15 #address-cells = <2>;
16 #size-cells = <0>;
22 enable-method = "spin-table";
23 cpu-release-addr = <0x1 0x0000fff8>;
[all …]
Dapm-storm.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * dts file for AppliedMicro (APM) X-Gene Storm SOC
9 compatible = "apm,xgene-storm";
10 interrupt-parent = <&gic>;
11 #address-cells = <2>;
12 #size-cells = <2>;
15 #address-cells = <2>;
16 #size-cells = <0>;
22 enable-method = "spin-table";
23 cpu-release-addr = <0x1 0x0000fff8>;
[all …]
/Linux-v5.10/arch/powerpc/platforms/44x/
Diss4xx.c1 // SPDX-License-Identifier: GPL-2.0-or-later
9 * Copyright 2002-2005 MontaVista Software Inc.
12 * Copyright (c) 2003-2005 Zultys Technologies
54 for_each_node_with_property(np, "interrupt-controller") { in iss4xx_init_irq()
66 } else if (of_device_is_compatible(np, "chrp,open-pic")) { in iss4xx_init_irq()
68 * device-tree, just pass 0 to all arguments in iss4xx_init_irq()
94 /* Assume spin table. We could test for the enable-method in in smp_iss4xx_kick_cpu()
95 * the device-tree but currently there's little point as it's in smp_iss4xx_kick_cpu()
98 spin_table_addr_prop = of_get_property(cpunode, "cpu-release-addr", in smp_iss4xx_kick_cpu()
101 pr_err("CPU%d: Can't start, missing cpu-release-addr !\n", cpu); in smp_iss4xx_kick_cpu()
[all …]
Dppc476.c1 // SPDX-License-Identifier: GPL-2.0-or-later
10 * Copyright 2002-2005 MontaVista Software Inc.
13 * Copyright (c) 2003-2005 Zultys Technologies
98 { "akebono-avr", 0 },
104 .name = "akebono-avr",
124 for_each_node_with_property(np, "interrupt-controller") { in ppc47x_init_irq()
132 if (of_device_is_compatible(np, "chrp,open-pic")) { in ppc47x_init_irq()
134 * device-tree, just pass 0 to all arguments in ppc47x_init_irq()
160 /* Assume spin table. We could test for the enable-method in in smp_ppc47x_kick_cpu()
161 * the device-tree but currently there's little point as it's in smp_ppc47x_kick_cpu()
[all …]
/Linux-v5.10/include/linux/
Drhashtable-types.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Resizable, Scalable, Concurrent Hash Table
29 * struct rhashtable_compare_arg - Key for the function rhashtable_compare
30 * @ht: Hash table
44 * struct rhashtable_params - Hash table construction parameters
70 * struct rhashtable - Hash table handle
71 * @tbl: Bucket table
73 * @max_elems: Maximum number of elements in table
77 * @mutex: Mutex to protect current/future table swapping
78 * @lock: Spin lock to protect walker list
[all …]
/Linux-v5.10/Documentation/kernel-hacking/
Dlocking.rst35 .. table:: Expected Results
37 +------------------------------------+------------------------------------+
41 +------------------------------------+------------------------------------+
43 +------------------------------------+------------------------------------+
45 +------------------------------------+------------------------------------+
47 +------------------------------------+------------------------------------+
49 +------------------------------------+------------------------------------+
51 +------------------------------------+------------------------------------+
55 .. table:: Possible Results
57 +------------------------------------+------------------------------------+
[all …]
/Linux-v5.10/net/tipc/
Dnet.c4 * Copyright (c) 1995-2006, 2014, Ericsson AB
5 * Copyright (c) 2005, 2010-2011, Wind River Systems
70 * are protected by node spin lock.
78 * - The tipc_port spin_lock. This is protecting each port instance
81 * corresponding reference table entry, which has the same life
84 * been added in the port instance, -to be used for unlocking
86 * - A read/write lock to protect the reference table itself (teg.c).
87 * (Nobody is using read-only access to this, so it can just as
89 * - A spin lock to protect the registry of kernel/driver users (reg.c)
90 * - A global spin_lock (tipc_port_lock), which only task is to ensure
[all …]

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