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/Linux-v6.1/Documentation/devicetree/bindings/spi/
Dnvidia,tegra210-quad.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/nvidia,tegra210-quad.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Tegra Quad SPI Controller
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jonathan Hunter <jonathanh@nvidia.com>
14 - $ref: "spi-controller.yaml#"
19 - nvidia,tegra210-qspi
20 - nvidia,tegra186-qspi
[all …]
Dspi-peripheral-props.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-peripheral-props.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Peripheral-specific properties for a SPI bus.
10 Many SPI controllers need to add properties to peripheral devices. They could
11 be common properties like spi-max-frequency, spi-cpha, etc. or they could be
13 need to be defined in the peripheral node because they are per-peripheral and
19 - Mark Brown <broonie@kernel.org>
27 - minimum: 0
[all …]
Dallwinner,sun6i-a31-spi.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/spi/allwinner,sun6i-a31-spi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A31 SPI Controller
10 - $ref: "spi-controller.yaml"
13 - Chen-Yu Tsai <wens@csie.org>
14 - Maxime Ripard <mripard@kernel.org>
17 "#address-cells": true
18 "#size-cells": true
[all …]
Dallwinner,sun4i-a10-spi.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/spi/allwinner,sun4i-a10-spi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A10 SPI Controller
10 - $ref: "spi-controller.yaml"
13 - Chen-Yu Tsai <wens@csie.org>
14 - Maxime Ripard <mripard@kernel.org>
17 "#address-cells": true
18 "#size-cells": true
[all …]
Datmel,quadspi.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/spi/atmel,quadspi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tudor Ambarus <tudor.ambarus@microchip.com>
13 - $ref: spi-controller.yaml#
18 - atmel,sama5d2-qspi
19 - microchip,sam9x60-qspi
20 - microchip,sama7g5-qspi
21 - microchip,sama7g5-ospi
[all …]
Dspi-nxp-fspi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-nxp-fspi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Han Xu <han.xu@nxp.com>
11 - Kuldeep Singh <singh.kuldeep87k@gmail.com>
14 - $ref: "spi-controller.yaml#"
19 - nxp,imx8dxl-fspi
20 - nxp,imx8mm-fspi
21 - nxp,imx8mp-fspi
[all …]
Dmediatek,spi-mtk-snfi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/mediatek,spi-mtk-snfi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: SPI-NAND flash controller for MediaTek ARM SoCs
10 - Chuanhong Guo <gch981213@gmail.com>
13 The Mediatek SPI-NAND flash controller is an extended version of
14 the Mediatek NAND flash controller. It can perform standard SPI
15 instructions with one continuous write and one read for up-to 0xa0
16 bytes. It also supports typical SPI-NAND page cache operations
[all …]
Drockchip-sfc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/rockchip-sfc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Heiko Stuebner <heiko@sntech.de>
11 - Chris Morgan <macromorgan@hotmail.com>
14 - $ref: spi-controller.yaml#
32 - description: Bus Clock
33 - description: Module Clock
35 clock-names:
[all …]
/Linux-v6.1/arch/arm64/boot/dts/freescale/
Dfsl-ls1088a-qds.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
11 /dts-v1/;
13 #include "fsl-ls1088a.dtsi"
17 compatible = "fsl,ls1088a-qds", "fsl,ls1088a";
21 bus-num = <0>;
25 #address-cells = <1>;
26 #size-cells = <1>;
27 compatible = "jedec,spi-nor";
29 spi-max-frequency = <1000000>;
33 #address-cells = <1>;
[all …]
Dfsl-ls2081a-rdb.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
11 /dts-v1/;
13 #include "fsl-ls2088a.dtsi"
17 compatible = "fsl,ls2081a-rdb", "fsl,ls2081a";
25 stdout-path = "serial1:115200n8";
33 compatible = "jedec,spi-nor";
34 #address-cells = <1>;
35 #size-cells = <1>;
36 spi-max-frequency = <3000000>;
51 #address-cells = <1>;
[all …]
Dfsl-ls1046a-rdb.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Freescale Layerscape-1046A family SoC.
6 * Copyright 2019-2020 NXP
11 /dts-v1/;
13 #include "fsl-ls1046a.dtsi"
17 compatible = "fsl,ls1046a-rdb", "fsl,ls1046a";
27 stdout-path = "serial0:115200n8";
40 mmc-hs200-1_8v;
41 sd-uhs-sdr104;
42 sd-uhs-sdr50;
[all …]
Dfsl-lx2160a-rdb.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
5 // Copyright 2018-2020 NXP
7 /dts-v1/;
9 #include "fsl-lx2160a.dtsi"
13 compatible = "fsl,lx2160a-rdb", "fsl,lx2160a";
23 stdout-path = "serial0:115200n8";
26 sb_3v3: regulator-sb3v3 {
27 compatible = "regulator-fixed";
28 regulator-name = "MC34717-3.3VSB";
29 regulator-min-microvolt = <3300000>;
[all …]
Dfsl-ls208xa-qds.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
14 phy-handle = <&mdio0_phy12>;
15 phy-connection-type = "sgmii";
19 phy-handle = <&mdio0_phy13>;
20 phy-connection-type = "sgmii";
24 phy-handle = <&mdio0_phy14>;
25 phy-connection-type = "sgmii";
29 phy-handle = <&mdio0_phy15>;
30 phy-connection-type = "sgmii";
34 mmc-hs200-1_8v;
[all …]
Dfsl-ls1088a-ten64.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 * Based on fsl-ls1088a-rdb.dts
5 * Copyright 2017-2020 NXP
6 * Copyright 2019-2021 Traverse Technologies
11 /dts-v1/;
13 #include "fsl-ls1088a.dtsi"
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/input/input.h>
28 stdout-path = "serial0:115200n8";
32 compatible = "gpio-keys";
[all …]
Dfsl-ls1088a-rdb.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * Copyright 2017-2020 NXP
11 /dts-v1/;
13 #include "fsl-ls1088a.dtsi"
17 compatible = "fsl,ls1088a-rdb", "fsl,ls1088a";
21 phy-handle = <&mdio2_aquantia_phy>;
22 phy-connection-type = "10gbase-r";
23 pcs-handle = <&pcs2>;
27 phy-handle = <&mdio1_phy5>;
28 phy-connection-type = "qsgmii";
[all …]
Dfsl-ls1012a-frwy.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
10 /dts-v1/;
12 #include "fsl-ls1012a.dtsi"
16 compatible = "fsl,ls1012a-frwy", "fsl,ls1012a";
35 compatible = "jedec,spi-nor";
36 #address-cells = <1>;
37 #size-cells = <1>;
38 m25p,fast-read;
39 spi-max-frequency = <50000000>;
41 spi-rx-bus-width = <2>;
[all …]
/Linux-v6.1/arch/arm/boot/dts/
Dimx6sx-sdb.dts1 // SPDX-License-Identifier: GPL-2.0
5 #include "imx6sx-sdb.dtsi"
12 clock-frequency = <100000>;
13 pinctrl-names = "default";
14 pinctrl-0 = <&pinctrl_i2c1>;
23 regulator-min-microvolt = <300000>;
24 regulator-max-microvolt = <1875000>;
25 regulator-boot-on;
26 regulator-always-on;
27 regulator-ramp-delay = <6250>;
[all …]
Daspeed-bmc-inventec-transformers.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
4 /dts-v1/;
6 #include "aspeed-g6.dtsi"
7 #include "aspeed-g6-pinctrl.dtsi"
8 #include <dt-bindings/i2c/i2c.h>
9 #include <dt-bindings/gpio/aspeed-gpio.h>
13 compatible = "inventec,transformer-bmc", "aspeed,ast2600";
20 stdout-path = &uart5;
30 compatible = "gpio-leds";
49 ethphy0: ethernet-phy@0 {
[all …]
Dimx6sx-sdb-reva.dts1 // SPDX-License-Identifier: GPL-2.0
5 #include "imx6sx-sdb.dtsi"
9 compatible = "fsl,imx6sx-sdb-reva", "fsl,imx6sx";
13 clock-frequency = <100000>;
14 pinctrl-names = "default";
15 pinctrl-0 = <&pinctrl_i2c1>;
24 regulator-min-microvolt = <300000>;
25 regulator-max-microvolt = <1875000>;
26 regulator-boot-on;
27 regulator-always-on;
[all …]
Dr8a7743-iwg20m.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the iWave-RZG1M-20M Qseven SOM
9 #include <dt-bindings/gpio/gpio.h>
25 compatible = "regulator-fixed";
26 regulator-name = "3P3V";
27 regulator-min-microvolt = <3300000>;
28 regulator-max-microvolt = <3300000>;
29 regulator-always-on;
30 regulator-boot-on;
35 clock-frequency = <20000000>;
[all …]
Dr8a7744-iwg20m.dtsi1 // SPDX-License-Identifier: GPL-2.0
9 #include <dt-bindings/gpio/gpio.h>
20 compatible = "regulator-fixed";
21 regulator-name = "3P3V";
22 regulator-min-microvolt = <3300000>;
23 regulator-max-microvolt = <3300000>;
24 regulator-always-on;
25 regulator-boot-on;
30 clock-frequency = <20000000>;
47 power-source = <3300>;
[all …]
Dr8a7745-iwg22m.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the iWave-RZG1E-G22M SODIMM SOM
9 #include <dt-bindings/gpio/gpio.h>
20 compatible = "regulator-fixed";
21 regulator-name = "3P3V";
22 regulator-min-microvolt = <3300000>;
23 regulator-max-microvolt = <3300000>;
24 regulator-always-on;
25 regulator-boot-on;
34 clock-frequency = <20000000>;
[all …]
Dat91-sama5d2_icp.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * at91-sama5d2_icp.dts - Device Tree file for SAMA5D2-ICP board
11 /dts-v1/;
13 #include "sama5d2-pinfunc.h"
14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/input/input.h>
16 #include <dt-bindings/mfd/atmel-flexcom.h>
19 model = "Microchip SAMA5D2-ICP";
20 compatible = "microchip,sama5d2-icp", "atmel,sama5d27", "atmel,sama5d2", "atmel,sama5";
23 serial0 = &uart0; /* debug uart0 + mikro BUS 1 */
[all …]
/Linux-v6.1/arch/arm64/boot/dts/nvidia/
Dtegra234-p3701-0000.dtsi1 // SPDX-License-Identifier: GPL-2.0
7 compatible = "nvidia,p3701-0000", "nvidia,tegra234";
9 vdd_1v8_ls: regulator-vdd-1v8-ls {
10 compatible = "regulator-fixed";
11 regulator-name = "VDD_1V8_LS";
12 regulator-min-microvolt = <1800000>;
13 regulator-max-microvolt = <1800000>;
14 regulator-always-on;
17 vdd_1v8_ao: regulator-vdd-1v8-ao {
18 compatible = "regulator-fixed";
[all …]
/Linux-v6.1/arch/arm64/boot/dts/xilinx/
Dzynqmp-zc1275-revA.dts1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2017 - 2021, Xilinx, Inc.
11 /dts-v1/;
14 #include "zynqmp-clk-ccf.dtsi"
18 compatible = "xlnx,zynqmp-zc1275-revA", "xlnx,zynqmp-zc1275", "xlnx,zynqmp";
28 stdout-path = "serial0:115200n8";
48 compatible = "m25p80", "jedec,spi-nor";
50 spi-tx-bus-width = <1>;
51 spi-rx-bus-width = <4>;
52 spi-max-frequency = <108000000>;

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