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/Linux-v5.15/drivers/mtd/spi-nor/
DMakefile1 # SPDX-License-Identifier: GPL-2.0
3 spi-nor-objs := core.o sfdp.o swp.o otp.o sysfs.o
4 spi-nor-objs += atmel.o
5 spi-nor-objs += catalyst.o
6 spi-nor-objs += eon.o
7 spi-nor-objs += esmt.o
8 spi-nor-objs += everspin.o
9 spi-nor-objs += fujitsu.o
10 spi-nor-objs += gigadevice.o
11 spi-nor-objs += intel.o
[all …]
Dcore.h1 /* SPDX-License-Identifier: GPL-2.0 */
51 /* Dual SPI */
57 /* Quad SPI */
63 /* Octal SPI */
76 /* Quad SPI */
81 /* Octal SPI */
91 * struct spi_nor_erase_type - Structure to describe a SPI NOR erase type
97 * @opcode: the SPI command op code to erase the sector/block.
112 * struct spi_nor_erase_command - Used for non-uniform erases
115 * are run-length encoded.
[all …]
Dsysfs.c1 // SPDX-License-Identifier: GPL-2.0
3 #include <linux/mtd/spi-nor.h>
4 #include <linux/spi/spi.h>
5 #include <linux/spi/spi-mem.h>
13 struct spi_device *spi = to_spi_device(dev); in manufacturer_show() local
14 struct spi_mem *spimem = spi_get_drvdata(spi); in manufacturer_show()
15 struct spi_nor *nor = spi_mem_get_drvdata(spimem); in manufacturer_show() local
17 return sysfs_emit(buf, "%s\n", nor->manufacturer->name); in manufacturer_show()
24 struct spi_device *spi = to_spi_device(dev); in partname_show() local
25 struct spi_mem *spimem = spi_get_drvdata(spi); in partname_show()
[all …]
Dcore.c1 // SPDX-License-Identifier: GPL-2.0
22 #include <linux/spi/flash.h>
23 #include <linux/mtd/spi-nor.h>
30 * For everything but full-chip erase; probably could be much smaller, but kept
36 * For full-chip erase, calibrated to a 2MB flash (M25P16); should be scaled up
47 * spi_nor_get_cmd_ext() - Get the command opcode extension based on the
49 * @nor: pointer to a 'struct spi_nor'
57 static u8 spi_nor_get_cmd_ext(const struct spi_nor *nor, in spi_nor_get_cmd_ext() argument
60 switch (nor->cmd_ext_type) { in spi_nor_get_cmd_ext()
62 return ~op->cmd.opcode; in spi_nor_get_cmd_ext()
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DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 tristate "SPI NOR device support"
8 This is the framework for the SPI NOR which can be used by the SPI
9 device drivers and the SPI NOR device driver.
34 This option disables the software write protection on any SPI
35 flashes at boot-up.
41 of your SPI flash. This is only to keep backwards compatibility.
46 Some SPI flashes have volatile block protection bits, ie. after a
47 power-up or a reset the flash is software write protected by
51 of flashes while keeping it enabled for any other SPI flashes
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/Linux-v5.15/Documentation/devicetree/bindings/spi/
Dmediatek,spi-mtk-nor.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/mediatek,spi-mtk-nor.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Serial NOR flash controller for MediaTek ARM SoCs
10 - Bayi Cheng <bayi.cheng@mediatek.com>
11 - Chuanhong Guo <gch981213@gmail.com>
14 This spi controller support single, dual, or quad mode transfer for
15 SPI NOR flash. There should be only one spi slave device following
16 generic spi bindings. It's not recommended to use this controller
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/Linux-v5.15/Documentation/driver-api/mtd/
Dspi-nor.rst2 SPI NOR framework
5 Part I - Why do we need this framework?
6 ---------------------------------------
8 SPI bus controllers (drivers/spi/) only deal with streams of bytes; the bus
11 arbitrary streams of bytes, but rather are designed specifically for SPI NOR.
13 In particular, Freescale's QuadSPI controller must know the NOR commands to
14 find the right LUT sequence. Unfortunately, the SPI subsystem has no notion of
15 opcodes, addresses, or data payloads; a SPI controller simply knows to send or
18 details of the SPI NOR protocol.
20 Part II - How does the framework work?
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/Linux-v5.15/include/linux/mtd/
Dspi-nor.h1 /* SPDX-License-Identifier: GPL-2.0+ */
12 #include <linux/spi/spi-mem.h>
19 * requires a 4-byte (32-bit) address.
31 #define SPINOR_OP_READ_1_1_2 0x3b /* Read data bytes (Dual Output SPI) */
32 #define SPINOR_OP_READ_1_2_2 0xbb /* Read data bytes (Dual I/O SPI) */
33 #define SPINOR_OP_READ_1_1_4 0x6b /* Read data bytes (Quad Output SPI) */
34 #define SPINOR_OP_READ_1_4_4 0xeb /* Read data bytes (Quad I/O SPI) */
35 #define SPINOR_OP_READ_1_1_8 0x8b /* Read data bytes (Octal Output SPI) */
36 #define SPINOR_OP_READ_1_8_8 0xcb /* Read data bytes (Octal I/O SPI) */
58 /* 4-byte address opcodes - used on Spansion and some Macronix flashes. */
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/Linux-v5.15/Documentation/ABI/testing/
Dsysfs-bus-spi-devices-spi-nor1 What: /sys/bus/spi/devices/.../spi-nor/jedec_id
4 Contact: linux-mtd@lists.infradead.org
5 Description: (RO) The JEDEC ID of the SPI NOR flash as reported by the
9 What: /sys/bus/spi/devices/.../spi-nor/manufacturer
12 Contact: linux-mtd@lists.infradead.org
13 Description: (RO) Manufacturer of the SPI NOR flash.
16 What: /sys/bus/spi/devices/.../spi-nor/partname
19 Contact: linux-mtd@lists.infradead.org
20 Description: (RO) Part name of the SPI NOR flash.
23 What: /sys/bus/spi/devices/.../spi-nor/sfdp
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/Linux-v5.15/Documentation/devicetree/bindings/mtd/
Dhisilicon,fmc-spi-nor.txt1 HiSilicon SPI-NOR Flash Controller
4 - compatible : Should be "hisilicon,fmc-spi-nor" and one of the following strings:
5 "hisilicon,hi3519-spi-nor"
6 - address-cells : Should be 1.
7 - size-cells : Should be 0.
8 - reg : Offset and length of the register set for the controller device.
9 - reg-names : Must include the following two entries: "control", "memory".
10 - clocks : handle to spi-nor flash controller clock.
13 spi-nor-controller@10000000 {
14 compatible = "hisilicon,hi3519-spi-nor", "hisilicon,fmc-spi-nor";
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Djedec,spi-nor.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/mtd/jedec,spi-nor.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: SPI NOR flash ST M25Pxx (and similar) serial flash chips
10 - Rob Herring <robh@kernel.org>
13 - $ref: "mtd.yaml#"
18 - items:
19 - pattern: "^((((micron|spansion|st),)?\
32 - const: jedec,spi-nor
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Daspeed-smc.txt2 * Aspeed SPI Flash Memory Controller
5 three chip selects, two of which are always of SPI type and the third
6 can be SPI or NOR type flash. These bindings only describe SPI.
8 The two SPI flash memory controllers in the AST2500 each support two
12 - compatible : Should be one of
13 "aspeed,ast2400-fmc" for the AST2400 Firmware Memory Controller
14 "aspeed,ast2400-spi" for the AST2400 SPI Flash memory Controller
15 "aspeed,ast2500-fmc" for the AST2500 Firmware Memory Controller
16 "aspeed,ast2500-spi" for the AST2500 SPI flash memory controllers
18 - reg : the first contains the control register location and length,
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/Linux-v5.15/arch/arm64/boot/dts/freescale/
Dfsl-ls1088a-qds.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
11 /dts-v1/;
13 #include "fsl-ls1088a.dtsi"
17 compatible = "fsl,ls1088a-qds", "fsl,ls1088a";
21 bus-num = <0>;
25 #address-cells = <1>;
26 #size-cells = <1>;
27 compatible = "jedec,spi-nor";
29 spi-max-frequency = <1000000>;
33 #address-cells = <1>;
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Dfsl-ls1028a-qds.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
11 /dts-v1/;
13 #include "fsl-ls1028a.dtsi"
17 compatible = "fsl,ls1028a-qds", "fsl,ls1028a";
32 stdout-path = "serial0:115200n8";
40 sys_mclk: clock-mclk {
41 compatible = "fixed-clock";
42 #clock-cells = <0>;
43 clock-frequency = <25000000>;
46 reg_1p8v: regulator-1p8v {
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Dfsl-ls1046a-qds.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Freescale Layerscape-1046A family SoC.
11 /dts-v1/;
13 #include "fsl-ls1046a.dtsi"
17 compatible = "fsl,ls1046a-qds", "fsl,ls1046a";
31 stdout-path = "serial0:115200n8";
36 bus-num = <0>;
40 #address-cells = <1>;
41 #size-cells = <1>;
42 compatible = "n25q128a11", "jedec,spi-nor";
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Dfsl-ls1012a-qds.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 /dts-v1/;
10 #include "fsl-ls1012a.dtsi"
14 compatible = "fsl,ls1012a-qds", "fsl,ls1012a";
21 sys_mclk: clock-mclk {
22 compatible = "fixed-clock";
23 #clock-cells = <0>;
24 clock-frequency = <24576000>;
27 reg_3p3v: regulator-3p3v {
28 compatible = "regulator-fixed";
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Dfsl-lx2160a-qds.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 /dts-v1/;
9 #include "fsl-lx2160a.dtsi"
13 compatible = "fsl,lx2160a-qds", "fsl,lx2160a";
23 stdout-path = "serial0:115200n8";
26 sb_3v3: regulator-sb3v3 {
27 compatible = "regulator-fixed";
28 regulator-name = "MC34717-3.3VSB";
29 regulator-min-microvolt = <3300000>;
30 regulator-max-microvolt = <3300000>;
[all …]
/Linux-v5.15/drivers/mtd/spi-nor/controllers/
Dnxp-spifi.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * SPI NOR driver for NXP SPI Flash Interface (SPIFI)
18 #include <linux/mtd/spi-nor.h>
22 #include <linux/spi/spi.h>
59 struct spi_nor nor; member
69 ret = readb_poll_timeout(spifi->io_base + SPIFI_STAT, stat, in nxp_spifi_wait_for_cmd()
72 dev_warn(spifi->dev, "command timed out\n"); in nxp_spifi_wait_for_cmd()
82 writel(SPIFI_STAT_RESET, spifi->io_base + SPIFI_STAT); in nxp_spifi_reset()
83 ret = readb_poll_timeout(spifi->io_base + SPIFI_STAT, stat, in nxp_spifi_reset()
86 dev_warn(spifi->dev, "state reset timed out\n"); in nxp_spifi_reset()
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DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 tristate "Aspeed flash controllers in SPI mode"
8 in the Aspeed AST2500/AST2400 SoCs when attached to SPI NOR chips,
9 and support for the SPI flash memory controller (SPI) for
10 the host firmware. The implementation only supports SPI NOR.
13 tristate "Hisilicon FMC SPI NOR Flash Controller(SFC)"
17 This enables support for HiSilicon FMC SPI NOR flash controller.
20 tristate "NXP SPI Flash Interface (SPIFI)"
24 Enable support for the NXP LPC SPI Flash Interface controller.
26 SPIFI is a specialized controller for connecting serial SPI
[all …]
Daspeed-smc.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (c) 2015-2016, IBM Corporation.
15 #include <linux/mtd/spi-nor.h>
21 #define DEVICE_NAME "aspeed-smc"
24 * The driver only support SPI flash
100 struct spi_nor nor; member
109 void __iomem *ahb_base; /* per-chip windows resource */
116 * SPI Flash Configuration Register (AST2500 SPI)
119 * CE0 and CE1 can only be of type SPI. CE2 can be of type NOR but the
156 #define CONTROL_IO_ADDRESS_4B BIT(13) /* AST2400 SPI */
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Dhisi-sfc.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * HiSilicon FMC SPI NOR flash controller driver
5 * Copyright (c) 2015-2016 HiSilicon Technologies Co., Ltd.
9 #include <linux/dma-mapping.h>
13 #include <linux/mtd/spi-nor.h>
64 #define HIFMC_DMA_MASK (HIFMC_DMA_MAX_LEN - 1)
99 struct spi_nor *nor[HIFMC_MAX_CHIP_NUM]; member
107 return readl_poll_timeout(host->regbase + FMC_INT, reg, in hisi_spi_nor_wait_op_finish()
144 writel(reg, host->regbase + FMC_SPI_TIMING_CFG); in hisi_spi_nor_init()
147 static int hisi_spi_nor_prep(struct spi_nor *nor) in hisi_spi_nor_prep() argument
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/Linux-v5.15/arch/powerpc/boot/dts/fsl/
Dmpc8536ds.dtsi2 * MPC8536DS Device Tree Source stub (no addresses or top-level ranges)
13 * * Neither the name of Freescale Semiconductor nor the
36 nor@0,0 {
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "cfi-flash";
41 bank-width = <2>;
42 device-width = <1>;
46 label = "ramdisk-nor";
51 label = "diagnostic-nor";
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Dp1022ds.dtsi2 * P1022 DS Device Tree Source stub (no addresses or top-level ranges)
13 * * Neither the name of Freescale Semiconductor nor the
36 nor@0,0 {
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "cfi-flash";
41 bank-width = <2>;
42 device-width = <1>;
46 label = "ramdisk-nor";
47 read-only;
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Dp1024rdb.dtsi2 * P1024 RDB Device Tree Source stub (no addresses or top-level ranges)
13 * * Neither the name of Freescale Semiconductor nor the
36 nor@0,0 {
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "cfi-flash";
41 bank-width = <2>;
42 device-width = <1>;
48 label = "NOR Vitesse-7385 Firmware";
49 read-only;
[all …]
Dp1020rdb-pd.dts2 * P1020 RDB-PD Device Tree Source (32-bit address map)
13 * * Neither the name of Freescale Semiconductor nor the
35 /include/ "p1020si-pre.dtsi"
37 model = "fsl,P1020RDB-PD";
38 compatible = "fsl,P1020RDB-PD";
47 /* NOR, NAND flash, L2 switch and CPLD */
53 nor@0,0 {
54 #address-cells = <1>;
55 #size-cells = <1>;
56 compatible = "cfi-flash";
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