| /Linux-v6.1/Documentation/devicetree/bindings/reset/ |
| D | microchip,rst.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: "http://devicetree.org/schemas/reset/microchip,rst.yaml#"
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
7 title: Microchip Sparx5 Switch Reset Controller
10 - Steen Hegelund <steen.hegelund@microchip.com>
11 - Lars Povlsen <lars.povlsen@microchip.com>
14 The Microchip Sparx5 Switch provides reset control and implements the following
16 - One Time Switch Core Reset (Soft Reset)
20 pattern: "^reset-controller@[0-9a-f]+$"
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| /Linux-v6.1/drivers/net/ethernet/microchip/sparx5/ |
| D | sparx5_main.c | 1 // SPDX-License-Identifier: GPL-2.0+
2 /* Microchip Sparx5 Switch driver
6 * The Sparx5 Chip Register Model can be browsed at this location:
7 * https://github.com/microchip-ung/sparx-5_reginfo
25 #include <linux/reset.h>
33 ((SPX5_BUFFER_MEMORY / SPX5_BUFFER_CELL_SZ - 100) * (fraction) / 100)
214 static int sparx5_create_targets(struct sparx5 *sparx5) in sparx5_create_targets() argument
225 if (idx == iomap->range) { in sparx5_create_targets()
231 iores[idx] = platform_get_resource(sparx5->pdev, IORESOURCE_MEM, in sparx5_create_targets()
234 dev_err(sparx5->dev, "Invalid resource\n"); in sparx5_create_targets()
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| D | sparx5_port.c | 1 // SPDX-License-Identifier: GPL-2.0+
2 /* Microchip Sparx5 Switch driver
30 status->an_complete = true; in decode_sgmii_word()
32 status->link = false; in decode_sgmii_word()
36 switch (lp_abil & LPA_SGMII_SPD_MASK) { in decode_sgmii_word()
38 status->speed = SPEED_10; in decode_sgmii_word()
41 status->speed = SPEED_100; in decode_sgmii_word()
44 status->speed = SPEED_1000; in decode_sgmii_word()
47 status->link = false; in decode_sgmii_word()
51 status->duplex = DUPLEX_FULL; in decode_sgmii_word()
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| D | sparx5_packet.c | 1 // SPDX-License-Identifier: GPL-2.0+
2 /* Microchip Sparx5 Switch driver
19 #define XTR_VALID_BYTES(x) (4 - ((x) & 3))
23 void sparx5_xtr_flush(struct sparx5 *sparx5, u8 grp) in sparx5_xtr_flush() argument
26 spx5_wr(QS_XTR_FLUSH_FLUSH_SET(BIT(grp)), sparx5, QS_XTR_FLUSH); in sparx5_xtr_flush()
32 spx5_wr(0, sparx5, QS_XTR_FLUSH); in sparx5_xtr_flush()
39 /* FWD is bit 45-72 (28 bits), but we only read the 27 LSB for now */ in sparx5_ifh_parse()
46 info->src_port = FIELD_GET(GENMASK(7, 1), fwd); in sparx5_ifh_parse()
48 info->timestamp = in sparx5_ifh_parse()
55 static void sparx5_xtr_grp(struct sparx5 *sparx5, u8 grp, bool byte_swap) in sparx5_xtr_grp() argument
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| D | sparx5_fdma.c | 1 // SPDX-License-Identifier: GPL-2.0+
2 /* Microchip Sparx5 Switch driver
6 * The Sparx5 Chip Register Model can be browsed at this location:
7 * https://github.com/microchip-ung/sparx-5_reginfo
15 #include <linux/dma-mapping.h>
42 * +---------------------------+
44 * +---------------------------+
46 * +---------------------------+
48 * +---------------------------+
50 * +---------------------------+
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| D | sparx5_mactable.c | 1 // SPDX-License-Identifier: GPL-2.0+
2 /* Microchip Sparx5 Switch driver
44 static int sparx5_mact_get_status(struct sparx5 *sparx5) in sparx5_mact_get_status() argument
46 return spx5_rd(sparx5, LRN_COMMON_ACCESS_CTRL); in sparx5_mact_get_status()
49 static int sparx5_mact_wait_for_completion(struct sparx5 *sparx5) in sparx5_mact_wait_for_completion() argument
54 sparx5, val, in sparx5_mact_wait_for_completion()
59 static void sparx5_mact_select(struct sparx5 *sparx5, in sparx5_mact_select() argument
76 spx5_wr(mach, sparx5, LRN_MAC_ACCESS_CFG_0); in sparx5_mact_select()
77 spx5_wr(macl, sparx5, LRN_MAC_ACCESS_CFG_1); in sparx5_mact_select()
80 int sparx5_mact_learn(struct sparx5 *sparx5, int pgid, in sparx5_mact_learn() argument
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| /Linux-v6.1/arch/arm64/boot/dts/microchip/ |
| D | sparx5.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/clock/microchip,sparx5.h>
11 compatible = "microchip,sparx5";
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <1>;
23 stdout-path = "serial0:115200n8";
27 #address-cells = <2>;
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| /Linux-v6.1/drivers/reset/ |
| D | reset-microchip-sparx5.c | 1 // SPDX-License-Identifier: GPL-2.0+
2 /* Microchip Sparx5 Switch Reset driver
6 * The Sparx5 Chip Register Model can be browsed at this location:
7 * https://github.com/microchip-ung/sparx-5_reginfo
14 #include <linux/reset-controller.h>
40 /* Make sure the core is PROTECTED from reset */ in sparx5_switch_reset()
41 regmap_update_bits(ctx->cpu_ctrl, ctx->props->protect_reg, in sparx5_switch_reset()
42 ctx->props->protect_bit, ctx->props->protect_bit); in sparx5_switch_reset()
44 /* Start soft reset */ in sparx5_switch_reset()
45 regmap_write(ctx->gcb_ctrl, ctx->props->reset_reg, in sparx5_switch_reset()
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| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
6 bool "Reset Controller Support"
9 Generic Reset Controller support.
11 This framework is designed to abstract reset handling of devices
12 via GPIOs or SoC-internal reset controller modules.
19 tristate "Altera Arria10 System Resource Reset"
22 This option enables support for the external reset functions for
26 bool "AR71xx Reset Driver" if COMPILE_TEST
29 This enables the ATH79 reset controller driver that supports the
30 AR71xx SoC reset controller.
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| /Linux-v6.1/Documentation/devicetree/bindings/net/ |
| D | microchip,sparx5-switch.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/net/microchip,sparx5-switch.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip Sparx5 Ethernet switch controller
10 - Steen Hegelund <steen.hegelund@microchip.com>
11 - Lars Povlsen <lars.povlsen@microchip.com>
14 The SparX-5 Enterprise Ethernet switch family provides a rich set of
15 Enterprise switching features such as advanced TCAM-based VLAN and
17 security through TCAM-based frame processing using versatile content
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| /Linux-v6.1/Documentation/devicetree/bindings/pinctrl/ |
| D | microchip,sparx5-sgpio.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/microchip,sparx5-sgpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lars Povlsen <lars.povlsen@microchip.com>
21 pattern: "^gpio@[0-9a-f]+$"
25 - microchip,sparx5-sgpio
26 - mscc,ocelot-sgpio
27 - mscc,luton-sgpio
29 "#address-cells":
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| D | mscc,ocelot-pinctrl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mscc,ocelot-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexandre Belloni <alexandre.belloni@bootlin.com>
11 - Lars Povlsen <lars.povlsen@microchip.com>
16 - microchip,lan966x-pinctrl
17 - microchip,sparx5-pinctrl
18 - mscc,jaguar2-pinctrl
19 - mscc,luton-pinctrl
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| /Linux-v6.1/arch/arm/boot/dts/ |
| D | lan966x.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * lan966x.dtsi - Device Tree Include file for Microchip LAN966 family SoC
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/mfd/atmel-flexcom.h>
14 #include <dt-bindings/dma/at91.h>
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/clock/microchip,lan966x.h>
21 interrupt-parent = <&gic>;
22 #address-cells = <1>;
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| /Linux-v6.1/drivers/phy/microchip/ |
| D | sparx5_serdes.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* Microchip Sparx5 Switch SerDes driver
6 * The Sparx5 Chip Register Model can be browsed at this location:
7 * https://github.com/microchip-ung/sparx-5_reginfo
9 …* https://ww1.microchip.com/downloads/en/DeviceDoc/SparX-5_Family_L2L3_Enterprise_10G_Ethernet_Swi…
99 u8 if_width; /* UDL if-width: 10/16/20/32/64 */
102 bool no_pwrcycle:1; /* Omit initial power-cycle */
241 bool no_pwrcycle:1; /* Omit initial power-cycle */
614 switch (interface_width) { in sd25g28_get_iw_setting()
630 switch (interface_width) { in sd10g28_get_iw_setting()
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| /Linux-v6.1/drivers/pinctrl/ |
| D | pinctrl-microchip-sgpio.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
22 #include <linux/reset.h>
136 addr->port = pin / priv->bitcount; in sgpio_pin_to_addr()
137 addr->bit = pin % priv->bitcount; in sgpio_pin_to_addr()
142 return bit + port * priv->bitcount; in sgpio_addr_to_pin()
147 return (priv->properties->regoff[rno] + off) * in sgpio_get_addr()
148 regmap_get_reg_stride(priv->regs); in sgpio_get_addr()
157 ret = regmap_read(priv->regs, addr, &val); in sgpio_readl()
169 ret = regmap_write(priv->regs, addr, val); in sgpio_writel()
179 ret = regmap_update_bits(priv->regs, addr, clear | set, set); in sgpio_clrsetbits()
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| D | pinctrl-ocelot.c | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
5 * Author: <alexandre.belloni@free-electrons.com>
20 #include <linux/pinctrl/pinconf-generic.h>
23 #include <linux/reset.h>
1157 *groups = info->func[function].groups; in ocelot_get_function_groups()
1158 *num_groups = info->func[function].ngroups; in ocelot_get_function_groups()
1166 struct ocelot_pin_caps *p = info->desc->pins[pin].drv_data; in ocelot_pin_function_idx()
1170 if (function == p->functions[i]) in ocelot_pin_function_idx()
1173 if (function == p->a_functions[i]) in ocelot_pin_function_idx()
1177 return -1; in ocelot_pin_function_idx()
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| /Linux-v6.1/ |
| D | MAINTAINERS | 9 -------------------------
30 ``diff -u`` to make the patch easy to merge. Be prepared to get your
40 See Documentation/process/coding-style.rst for guidance here.
46 See Documentation/process/submitting-patches.rst for details.
57 include a Signed-off-by: line. The current version of this
59 Documentation/process/submitting-patches.rst.
70 that the bug would present a short-term risk to other users if it
76 Documentation/admin-guide/security-bugs.rst for details.
81 ---------------------------------------------------
97 W: *Web-page* with status/info
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