Searched +full:soc +full:- +full:controller (Results 1 – 25 of 1081) sorted by relevance
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| /Linux-v5.15/drivers/clk/samsung/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
4 bool "Samsung Exynos clock controller support" if COMPILE_TEST
16 bool "Samsung S3C64xx clock controller support" if COMPILE_TEST
19 Support for the clock controller present on the Samsung S3C64xx SoCs.
20 Choose Y here only if you build for this SoC.
23 bool "Samsung S5Pv210 clock controller support" if COMPILE_TEST
26 Support for the clock controller present on the Samsung S5Pv210 SoCs.
27 Choose Y here only if you build for this SoC.
30 bool "Samsung Exynos3250 clock controller support" if COMPILE_TEST
33 Support for the clock controller present on the Samsung
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| /Linux-v5.15/drivers/soc/renesas/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
3 bool "Renesas SoC driver support" if COMPILE_TEST && !ARCH_RENESAS
57 bool "ARM32 Platform support for R-Car E2"
63 bool "ARM32 Platform support for R-Car H1"
72 bool "ARM32 Platform support for R-Car H2"
80 bool "ARM32 Platform support for R-Car M1A"
85 bool "ARM32 Platform support for R-Car M2-N"
92 bool "ARM32 Platform support for R-Car M2-W"
99 bool "ARM32 Platform support for R-Car V2H"
105 bool "ARM32 Platform support for R-Mobile A1"
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| /Linux-v5.15/drivers/net/ethernet/stmicro/stmmac/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
3 tristate "STMicroelectronics Multi-Gigabit Ethernet driver"
38 If you have a controller with this interface, say Y or M here.
45 tristate "Support for snps,dwc-qos-ethernet.txt DT binding."
50 Support for chips using the snps,dwc-qos-ethernet.txt DT binding.
65 Support for Adaptrum Anarion GMAC Ethernet controller.
67 This selects the Anarion SoC glue layer support for the stmmac driver.
75 Support for ethernet controller on Ingenic SoCs.
79 MAC ethernet controller.
89 This selects the IPQ806x SoC glue layer support for the stmmac
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| /Linux-v5.15/drivers/pci/controller/dwc/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
23 bool "TI DRA7xx PCIe controller Host Mode"
31 Enables support for the PCIe controller in the DRA7xx SoC to work in
32 host mode. There are two instances of PCIe controller in DRA7xx.
33 This controller can work either as EP or RC. In order to enable
34 host-specific features PCI_DRA7XX_HOST must be selected and in order
35 to enable device-specific features PCI_DRA7XX_EP must be selected.
39 bool "TI DRA7xx PCIe controller Endpoint Mode"
46 Enables support for the PCIe controller in the DRA7xx SoC to work in
47 endpoint mode. There are two instances of PCIe controller in DRA7xx.
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| /Linux-v5.15/Documentation/devicetree/bindings/soc/litex/ |
| D | litex,soc-controller.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 ---
5 $id: "http://devicetree.org/schemas/soc/litex/litex,soc-controller.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
8 title: LiteX SoC Controller driver
11 This is the SoC Controller driver for the LiteX SoC Builder.
17 - Karol Gugala <kgugala@antmicro.com>
18 - Mateusz Holenko <mholenko@antmicro.com>
22 const: litex,soc-controller
28 - compatible
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| /Linux-v5.15/drivers/pinctrl/spear/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
21 bool "ST Microelectronics SPEAr300 SoC pin controller driver"
26 bool "ST Microelectronics SPEAr310 SoC pin controller driver"
32 bool "ST Microelectronics SPEAr320 SoC pin controller driver"
38 bool "ST Microelectronics SPEAr1310 SoC pin controller driver"
44 bool "ST Microelectronics SPEAr1340 SoC pin controller driver"
50 bool "SPEAr SoC PLGPIO Controller"
54 Say yes here to support PLGPIO controller on ST Microelectronics SPEAr
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| /Linux-v5.15/drivers/mmc/host/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
3 # MMC/SD host controller drivers
6 comment "MMC/SD/SDIO Host Controller Drivers"
28 bool "Qualcomm Data Mover for SD Card Controller"
32 This selects the Qualcomm Data Mover lite/local on SD Card controller.
39 bool "STMicroelectronics STM32 SDMMC Controller"
43 This selects the STMicroelectronics STM32 SDMMC host controller.
59 tristate "Secure Digital Host Controller Interface support"
62 This selects the generic Secure Digital Host Controller Interface.
66 If you have a controller with this interface, say Y or M here. You
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| /Linux-v5.15/Documentation/devicetree/bindings/arm/keystone/ |
| D | ti,sci.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI-SCI controller device node bindings
10 - Nishanth Menon <nm@ti.com>
15 management of the System on Chip (SoC) system. These include various system
18 An example of such an SoC is K2G, which contains the system control hardware
19 block called Power Management Micro Controller (PMMC). This hardware block is
25 The TI-SCI node describes the Texas Instrument's System Controller entity node.
28 functionality as may be required for the SoC. This hierarchy also describes the
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| /Linux-v5.15/Documentation/devicetree/bindings/clock/ |
| D | samsung,s3c2410-clock.txt | 1 * Samsung S3C2410 Clock Controller
3 The S3C2410 clock controller generates and supplies clock to various controllers
4 within the SoC. The clock binding described here is applicable to the s3c2410,
9 - compatible: should be one of the following.
10 - "samsung,s3c2410-clock" - controller compatible with S3C2410 SoC.
11 - "samsung,s3c2440-clock" - controller compatible with S3C2440 SoC.
12 - "samsung,s3c2442-clock" - controller compatible with S3C2442 SoC.
13 - reg: physical base address of the controller and length of memory mapped
15 - #clock-cells: should be 1.
19 on a particular SoC.
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| D | samsung,s3c2443-clock.txt | 1 * Samsung S3C2443 Clock Controller
3 The S3C2443 clock controller generates and supplies clock to various controllers
4 within the SoC. The clock binding described here is applicable to all SoCs in
9 - compatible: should be one of the following.
10 - "samsung,s3c2416-clock" - controller compatible with S3C2416 SoC.
11 - "samsung,s3c2443-clock" - controller compatible with S3C2443 SoC.
12 - "samsung,s3c2450-clock" - controller compatible with S3C2450 SoC.
13 - reg: physical base address of the controller and length of memory mapped
15 - #clock-cells: should be 1.
19 on a particular SoC.
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| D | amlogic,gxbb-clkc.txt | 3 The Amlogic GXBB clock controller generates and supplies clock to various
4 controllers within the SoC.
8 - compatible: should be:
9 "amlogic,gxbb-clkc" for GXBB SoC,
10 "amlogic,gxl-clkc" for GXL and GXM SoC,
11 "amlogic,axg-clkc" for AXG SoC.
12 "amlogic,g12a-clkc" for G12A SoC.
13 "amlogic,g12b-clkc" for G12B SoC.
14 "amlogic,sm1-clkc" for SM1 SoC.
15 - clocks : list of clock phandle, one for each entry clock-names.
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| D | samsung,s5pv210-clock.txt | 1 * Samsung S5P6442/S5PC110/S5PV210 Clock Controller
4 controller, which generates and supplies clock to various controllers
5 within the SoC.
9 - compatible: should be one of following:
10 - "samsung,s5pv210-clock" : for clock controller of Samsung
12 - "samsung,s5p6442-clock" : for clock controller of Samsung
13 S5P6442 SoC.
15 - reg: physical base address of the controller and length of memory mapped
18 - #clock-cells: should be 1.
21 dt-bindings/clock/s5pv210.h header and can be used in device tree sources.
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| D | rockchip,rk3128-cru.txt | 3 The RK3126/RK3128 clock controller generates and supplies clock to various
4 controllers within the SoC and also implements a reset controller for SoC
9 - compatible: should be "rockchip,rk3126-cru" or "rockchip,rk3128-cru"
10 "rockchip,rk3126-cru" - controller compatible with RK3126 SoC.
11 "rockchip,rk3128-cru" - controller compatible with RK3128 SoC.
12 - reg: physical base address of the controller and length of memory mapped
14 - #clock-cells: should be 1.
15 - #reset-cells: should be 1.
19 - rockchip,grf: phandle to the syscon managing the "general register files"
24 preprocessor macros in the dt-bindings/clock/rk3128-cru.h headers and can be
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| D | samsung,s3c64xx-clock.txt | 1 * Samsung S3C64xx Clock Controller
3 The S3C64xx clock controller generates and supplies clock to various controllers
4 within the SoC. The clock binding described here is applicable to all SoCs in
9 - compatible: should be one of the following.
10 - "samsung,s3c6400-clock" - controller compatible with S3C6400 SoC.
11 - "samsung,s3c6410-clock" - controller compatible with S3C6410 SoC.
13 - reg: physical base address of the controller and length of memory mapped
16 - #clock-cells: should be 1.
20 on a particular S3C64xx SoC and this is specified where applicable.
23 dt-bindings/clock/samsung,s3c64xx-clock.h header and can be used in device
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| /Linux-v5.15/Documentation/devicetree/bindings/edac/ |
| D | apm-xgene-edac.txt | 1 * APM X-Gene SoC EDAC node
3 EDAC node is defined to describe on-chip error detection and correction.
6 memory controller - Memory controller
7 PMD (L1/L2) - Processor module unit (PMD) L1/L2 cache
8 L3 - L3 cache controller
9 SoC - SoC IP's such as Ethernet, SATA, and etc
14 - compatible : Shall be "apm,xgene-edac".
15 - regmap-csw : Regmap of the CPU switch fabric (CSW) resource.
16 - regmap-mcba : Regmap of the MCB-A (memory bridge) resource.
17 - regmap-mcbb : Regmap of the MCB-B (memory bridge) resource.
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| /Linux-v5.15/Documentation/devicetree/bindings/pinctrl/ |
| D | berlin,pinctrl.txt | 1 * Pin-controller driver for the Marvell Berlin SoCs
3 Pin control registers are part of both chip controller and system
4 controller register sets. Pin controller nodes should be a sub-node of
5 either the chip controller or system controller node. The pins
9 A pin-controller node should contain subnodes representing the pin group
14 is called a 'function' in the pin-controller subsystem.
17 - compatible: should be one of:
18 "marvell,berlin2-soc-pinctrl",
19 "marvell,berlin2-system-pinctrl",
20 "marvell,berlin2cd-soc-pinctrl",
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| D | brcm,iproc-gpio.txt | 1 Broadcom iProc GPIO/PINCONF Controller
5 - compatible:
6 "brcm,iproc-gpio" for the generic iProc based GPIO controller IP that
7 supports full-featured pinctrl and GPIO functions used in various iProc
10 May contain an SoC-specific compatibility string to accommodate any
11 SoC-specific features
13 "brcm,cygnus-ccm-gpio", "brcm,cygnus-asiu-gpio", or
14 "brcm,cygnus-crmu-gpio" for Cygnus SoCs
16 "brcm,iproc-nsp-gpio" for the iProc NSP SoC that has drive strength support
19 "brcm,iproc-stingray-gpio" for the iProc Stingray SoC that has the general
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| /Linux-v5.15/drivers/pci/controller/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
3 menu "PCI controller drivers"
7 bool "Marvell EBU PCIe controller"
15 tristate "Aardvark PCIe controller"
21 Add support for Aardvark 64bit PCIe Host Controller. This
22 controller is part of the South Bridge of the Marvel Armada
23 3700 SoC.
31 NWL PCIe controller. The controller can act as Root Port
36 bool "Faraday Technology FTPCI100 PCI controller"
41 bool "Intel IXP4xx PCI controller"
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| /Linux-v5.15/Documentation/devicetree/bindings/soc/microchip/ |
| D | microchip,polarfire-soc-sys-controller.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: "http://devicetree.org/schemas/soc/microchip/microchip,polarfire-soc-sys-controller.yaml#"
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
7 title: Microchip PolarFire SoC (MPFS) MSS (microprocessor subsystem) system controller
10 - Conor Dooley <conor.dooley@microchip.com>
13 The PolarFire SoC system controller is communicated with via a mailbox.
22 const: microchip,polarfire-soc-sys-controller
25 - compatible
26 - mboxes
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| /Linux-v5.15/Documentation/devicetree/bindings/gpio/ |
| D | gpio-mpc8xxx.txt | 1 * Freescale MPC512x/MPC8xxx/QorIQ/Layerscape GPIO controller
4 - compatible : Should be "fsl,<soc>-gpio"
5 The following <soc>s are known to be supported:
8 - reg : Address and length of the register set for the device
9 - interrupts : Should be the port interrupt shared by all 32 pins.
10 - #gpio-cells : Should be two. The first cell is the pin number and
16 - little-endian : GPIO registers are used as little endian. If not
19 Example of gpio-controller node for a mpc5125 SoC:
22 compatible = "fsl,mpc5125-gpio";
23 #gpio-cells = <2>;
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| D | 8xxx_gpio.txt | 3 This is for the non-QE/CPM/GUTs GPIO controllers as found on
6 Every GPIO controller node must have #gpio-cells property defined,
7 this information will be used to translate gpio-specifiers.
11 The GPIO module usually is connected to the SoC's internal interrupt
12 controller, see bindings/interrupt-controller/interrupts.txt (the
16 The GPIO module may serve as another interrupt controller (cascaded to
17 the SoC's internal interrupt controller). See the interrupt controller
18 nodes section in bindings/interrupt-controller/interrupts.txt for
22 - compatible: "fsl,<chip>-gpio" followed by "fsl,mpc8349-gpio"
23 for 83xx, "fsl,mpc8572-gpio" for 85xx, or
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| /Linux-v5.15/drivers/gpu/drm/sun4i/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
13 Choose this option if you have an Allwinner SoC with a
15 sun4i-drm.
20 tristate "Allwinner A10 HDMI Controller Support"
23 Choose this option if you have an Allwinner SoC with an HDMI
24 controller.
32 Choose this option if you have an Allwinner SoC with an HDMI
33 controller and want to use CEC.
39 Choose this option if you have an Allwinner SoC with the
42 selected the module will be called sun4i-backend.
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| /Linux-v5.15/Documentation/devicetree/bindings/mfd/ |
| D | canaan,k210-sysctl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mfd/canaan,k210-sysctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Canaan Kendryte K210 System Controller Device Tree Bindings
10 - Damien Le Moal <damien.lemoal@wdc.com>
13 Canaan Inc. Kendryte K210 SoC system controller which provides a
15 domains of the SoC.
20 - const: canaan,k210-sysctl
21 - const: syscon
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| /Linux-v5.15/drivers/reset/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
6 bool "Reset Controller Support"
9 Generic Reset Controller support.
12 via GPIOs or SoC-internal reset controller modules.
29 This enables the ATH79 reset controller driver that supports the
30 AR71xx SoC reset controller.
36 This enables the reset controller driver for AXS10x.
39 bool "BCM6345 Reset Controller"
43 This enables the reset controller driver for BCM6345 SoCs.
50 This enables the reset controller driver for Marvell Berlin SoCs.
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| /Linux-v5.15/drivers/usb/host/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
3 # USB Host Controller Drivers
5 comment "USB Host Controller Drivers"
11 The Cypress C67x00 (EZ-Host/EZ-OTG) chips are dual-role
14 Enable this option to support this chip in host controller mode.
24 The eXtensible Host Controller Interface (xHCI) is standard for USB 3.0
25 "SuperSpeed" host controller hardware.
28 module will be called xhci-hcd.
47 tristate "Support for additional Renesas xHCI controller with firmware"
49 Say 'Y' to enable the support for the Renesas xHCI controller with
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