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/Linux-v5.15/Documentation/devicetree/bindings/iommu/
Darm,smmu-v3.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/iommu/arm,smmu-v3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Will Deacon <will@kernel.org>
11 - Robin Murphy <Robin.Murphy@arm.com>
15 revisions, replacing the MMIO register interface with in-memory command
21 pattern: "^iommu@[0-9a-f]*"
23 const: arm,smmu-v3
32 interrupt-names:
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/Linux-v5.15/drivers/iommu/arm/arm-smmu-v3/
DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-$(CONFIG_ARM_SMMU_V3) += arm_smmu_v3.o
3 arm_smmu_v3-objs-y += arm-smmu-v3.o
4 arm_smmu_v3-objs-$(CONFIG_ARM_SMMU_V3_SVA) += arm-smmu-v3-sva.o
5 arm_smmu_v3-objs := $(arm_smmu_v3-objs-y)
Darm-smmu-v3.c1 // SPDX-License-Identifier: GPL-2.0
17 #include <linux/dma-iommu.h>
20 #include <linux/io-pgtable.h>
28 #include <linux/pci-ats.h>
33 #include "arm-smmu-v3.h"
34 #include "../../iommu-sva-lib.h"
39 …domain will report an abort back to the device and will not be allowed to pass through the SMMU.");
44 "Disable MSI-based polling for CMD_SYNC completion.");
86 { ARM_SMMU_OPT_SKIP_PREFETCH, "hisilicon,broken-prefetch-cmd" },
87 { ARM_SMMU_OPT_PAGE0_REGS_ONLY, "cavium,cn9900-broken-page1-regspace"},
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Darm-smmu-v3-sva.c1 // SPDX-License-Identifier: GPL-2.0
11 #include "arm-smmu-v3.h"
12 #include "../../iommu-sva-lib.h"
13 #include "../../io-pgtable-arm.h"
40 * Check if the CPU ASID is available on the SMMU side. If a private context
49 struct arm_smmu_device *smmu; in arm_smmu_share_asid() local
56 if (cd->mm) { in arm_smmu_share_asid()
57 if (WARN_ON(cd->mm != mm)) in arm_smmu_share_asid()
58 return ERR_PTR(-EINVAL); in arm_smmu_share_asid()
60 refcount_inc(&cd->refs); in arm_smmu_share_asid()
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/Linux-v5.15/Documentation/devicetree/bindings/display/
Darm,komeda.txt4 - compatible: Should be "arm,mali-d71"
5 - reg: Physical base address and length of the registers in the system
6 - interrupts: the interrupt line number of the device in the system
7 - clocks: A list of phandle + clock-specifier pairs, one for each entry
8 in 'clock-names'
9 - clock-names: A list of clock names. It should contain:
10 - "aclk": for the main processor clock
11 - #address-cells: Must be 1
12 - #size-cells: Must be 0
13 - iommus: configure the stream id to IOMMU, Must be configured if want to
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/Linux-v5.15/Documentation/devicetree/bindings/misc/
Dfsl,qoriq-mc.txt3 The Freescale Management Complex (fsl-mc) is a hardware resource
5 network-oriented packet processing applications. After the fsl-mc
12 For an overview of the DPAA2 architecture and fsl-mc bus see:
16 same hardware "isolation context" and a 10-bit value called an ICID
21 between ICIDs and IOMMUs, so an iommu-map property is used to define
28 For arm-smmu binding, see:
29 Documentation/devicetree/bindings/iommu/arm,smmu.yaml.
32 The msi-map property is used to associate the devices with both the ITS
36 Documentation/devicetree/bindings/interrupt-controller/msi.txt.
39 Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml.
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/Linux-v5.15/drivers/iommu/arm/
DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-y += arm-smmu/ arm-smmu-v3/
/Linux-v5.15/Documentation/devicetree/bindings/crypto/
Dhisilicon,hip07-sec.txt4 - compatible: Must contain one of
5 - "hisilicon,hip06-sec"
6 - "hisilicon,hip07-sec"
7 - reg: Memory addresses and lengths of the memory regions through which
11 Regions 2-18 have registers for the 16 individual queues which are isolated
13 - interrupts: Interrupt specifiers.
14 Refer to interrupt-controller/interrupts.txt for generic interrupt client node
19 - dma-coherent: The driver assumes coherent dma is possible.
22 - iommus: The SEC units are behind smmu-v3 iommus.
23 Refer to iommu/arm,smmu-v3.txt for more information.
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/Linux-v5.15/arch/arm64/boot/dts/nvidia/
Dtegra186.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra186-clock.h>
3 #include <dt-bindings/gpio/tegra186-gpio.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mailbox/tegra186-hsp.h>
6 #include <dt-bindings/memory/tegra186-mc.h>
7 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
8 #include <dt-bindings/power/tegra186-powergate.h>
9 #include <dt-bindings/reset/tegra186-reset.h>
10 #include <dt-bindings/thermal/tegra186-bpmp-thermal.h>
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Dtegra194.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra194-clock.h>
3 #include <dt-bindings/gpio/tegra194-gpio.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mailbox/tegra186-hsp.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
7 #include <dt-bindings/power/tegra194-powergate.h>
8 #include <dt-bindings/reset/tegra194-reset.h>
9 #include <dt-bindings/thermal/tegra194-bpmp-thermal.h>
10 #include <dt-bindings/memory/tegra194-mc.h>
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/Linux-v5.15/drivers/acpi/arm64/
Diort.c1 // SPDX-License-Identifier: GPL-2.0-only
21 #include <linux/dma-map-ops.h>
44 * iort_set_fwnode() - Create iort_fwnode and use it to register
61 return -ENOMEM; in iort_set_fwnode()
63 INIT_LIST_HEAD(&np->list); in iort_set_fwnode()
64 np->iort_node = iort_node; in iort_set_fwnode()
65 np->fwnode = fwnode; in iort_set_fwnode()
68 list_add_tail(&np->list, &iort_fwnode_list); in iort_set_fwnode()
75 * iort_get_fwnode() - Retrieve fwnode associated with an IORT node
77 * @node: IORT table node to be looked-up
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/Linux-v5.15/arch/arm64/boot/dts/arm/
Dfvp-base-revc.dts1 // SPDX-License-Identifier: GPL-2.0
5 * Architecture Envelope Model (AEM) ARMv8-A
11 /dts-v1/;
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 #include "rtsm_ve-motherboard.dtsi"
18 #include "rtsm_ve-motherboard-rs2.dtsi"
22 compatible = "arm,fvp-base-revc", "arm,vexpress";
23 interrupt-parent = <&gic>;
24 #address-cells = <2>;
25 #size-cells = <2>;
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/Linux-v5.15/arch/arm64/boot/dts/broadcom/stingray/
Dstingray.dtsi4 * Copyright(c) 2015-2017 Broadcom. All rights reserved.
33 #include <dt-bindings/interrupt-controller/arm-gic.h>
37 interrupt-parent = <&gic>;
38 #address-cells = <2>;
39 #size-cells = <2>;
42 #address-cells = <2>;
43 #size-cells = <0>;
47 compatible = "arm,cortex-a72";
49 enable-method = "psci";
50 next-level-cache = <&CLUSTER0_L2>;
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/Linux-v5.15/arch/arm64/boot/dts/hisilicon/
Dhip07.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 compatible = "hisilicon,hip07-d05";
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 compatible = "arm,psci-0.2";
22 #address-cells = <1>;
23 #size-cells = <0>;
25 cpu-map {
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Dhip06.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 compatible = "hisilicon,hip06-d03";
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 compatible = "arm,psci-0.2";
22 #address-cells = <1>;
23 #size-cells = <0>;
25 cpu-map {
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/Linux-v5.15/arch/arm64/boot/dts/freescale/
Dfsl-ls1088a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1088A family SoC.
5 * Copyright 2017-2020 NXP
10 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
26 #address-cells = <1>;
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Dfsl-ls208xa.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Freescale Layerscape-2080A family SoC.
6 * Copyright 2017-2020 NXP
12 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
13 #include <dt-bindings/thermal/thermal.h>
14 #include <dt-bindings/interrupt-controller/arm-gic.h>
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
32 #address-cells = <1>;
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Dfsl-lx2160a.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 // Device Tree Include file for Layerscape-LX2160A family SoC.
5 // Copyright 2018-2020 NXP
7 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
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Dfsl-ls1028a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1028A family SoC.
5 * Copyright 2018-2020 NXP
11 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/thermal/thermal.h>
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
22 #address-cells = <1>;
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/Linux-v5.15/drivers/iommu/
Dapple-dart.c1 // SPDX-License-Identifier: GPL-2.0-only
7 * Based on arm/arm-smmu/arm-ssmu.c and arm/arm-smmu-v3/arm-smmu-v3.c
10 * and on exynos-iommu.c
18 #include <linux/dma-iommu.h>
19 #include <linux/dma-mapping.h>
22 #include <linux/io-pgtable.h>
143 * @pgtbl_ops: pagetable ops allocated by io-pgtable
180 for (i = 0, stream_map = &(base)->stream_maps[0]; \
181 i < MAX_DARTS_PER_DEVICE && stream_map->dart; \
182 stream_map = &(base)->stream_maps[++i])
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/Linux-v5.15/drivers/perf/
Darm_smmuv3_pmu.c1 // SPDX-License-Identifier: GPL-2.0
9 * <phys_addr_page> is the physical page address of the SMMU PMCG wrapped
15 * filter_enable - 0 = no filtering, 1 = filtering enabled
16 * filter_span - 0 = exact match, 1 = pattern match
17 * filter_stream_id - pattern to filter against
19 * To match a partial StreamID where the X most-significant bits must match
20 * but the Y least-significant bits might differ, STREAMID is programmed
22 * STREAMID[Y - 1] == 0.
23 * STREAMID[Y - 2:0] == 1 (where Y > 1).
27 * Example: perf stat -e smmuv3_pmcg_ff88840/transaction,filter_enable=1,
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/Linux-v5.15/arch/arm64/boot/dts/qcom/
Dsdm630.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
7 #include <dt-bindings/clock/qcom,gcc-sdm660.h>
8 #include <dt-bindings/clock/qcom,gpucc-sdm660.h>
9 #include <dt-bindings/clock/qcom,mmcc-sdm660.h>
10 #include <dt-bindings/clock/qcom,rpmcc.h>
11 #include <dt-bindings/power/qcom-rpmpd.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/soc/qcom,apr.h>
17 interrupt-parent = <&intc>;
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Dmsm8996.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/clock/qcom,gcc-msm8996.h>
7 #include <dt-bindings/clock/qcom,mmcc-msm8996.h>
8 #include <dt-bindings/clock/qcom,rpmcc.h>
9 #include <dt-bindings/power/qcom-rpmpd.h>
10 #include <dt-bindings/soc/qcom,apr.h>
11 #include <dt-bindings/thermal/thermal.h>
14 interrupt-parent = <&intc>;
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Dmsm8998.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/clock/qcom,gcc-msm8998.h>
6 #include <dt-bindings/clock/qcom,gpucc-msm8998.h>
7 #include <dt-bindings/clock/qcom,rpmcc.h>
8 #include <dt-bindings/power/qcom-rpmpd.h>
9 #include <dt-bindings/gpio/gpio.h>
12 interrupt-parent = <&intc>;
14 qcom,msm-id = <292 0x0>;
16 #address-cells = <2>;
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/Linux-v5.15/drivers/pci/controller/dwc/
Dpcie-qcom.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
8 * Author: Stanimir Varbanov <svarbanov@mm-sol.com>
32 #include "pcie-designware.h"
202 #define to_qcom_pcie(x) dev_get_drvdata((x)->dev)
206 gpiod_set_value_cansleep(pcie->reset, 1); in qcom_ep_reset_assert()
214 gpiod_set_value_cansleep(pcie->reset, 0); in qcom_ep_reset_deassert()
223 if (pcie->ops->ltssm_enable) in qcom_pcie_start_link()
224 pcie->ops->ltssm_enable(pcie); in qcom_pcie_start_link()
234 val = readl(pcie->elbi + PCIE20_ELBI_SYS_CTRL); in qcom_pcie_2_1_0_ltssm_enable()
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