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/Linux-v6.1/Documentation/devicetree/bindings/media/i2c/
Dst,st-mipid02.txt1 STMicroelectronics MIPID02 CSI-2 to PARALLEL bridge
3 MIPID02 has two CSI-2 input ports, only one of those ports can be active at a
4 time. Active port input stream will be de-serialized and its content outputted
6 CSI-2 first input port is a dual lane 800Mbps per lane whereas CSI-2 second
7 input port is a single lane 800Mbps. Both ports support clock and data lane
8 polarity swap. First port also supports data lane swap.
11 YUV420 8-bit, YUV422 8-bit and YUV420 10-bit.
14 - compatible: shall be "st,st-mipid02"
15 - clocks: reference to the xclk input clock.
16 - clock-names: shall be "xclk".
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/phy/
Dphy-cadence-sierra.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: "http://devicetree.org/schemas/phy/phy-cadence-sierra.yaml#"
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
14 - Swapnil Jakhade <sjakhade@cadence.com>
15 - Yuti Amonkar <yamonkar@cadence.com>
20 - cdns,sierra-phy-t0
21 - ti,sierra-phy-t0
23 '#address-cells':
26 '#size-cells':
[all …]
Dphy-cadence-torrent.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: "http://devicetree.org/schemas/phy/phy-cadence-torrent.yaml#"
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
16 - Swapnil Jakhade <sjakhade@cadence.com>
17 - Yuti Amonkar <yamonkar@cadence.com>
22 - cdns,torrent-phy
23 - ti,j721e-serdes-10g
25 '#address-cells':
28 '#size-cells':
[all …]
Dqcom,qmp-usb-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,qmp-usb-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Vinod Koul <vkoul@kernel.org>
19 - qcom,ipq6018-qmp-usb3-phy
20 - qcom,ipq8074-qmp-usb3-phy
21 - qcom,msm8996-qmp-usb3-phy
22 - qcom,msm8998-qmp-usb3-phy
23 - qcom,qcm2290-qmp-usb3-phy
[all …]
Dqcom,qmp-ufs-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,qmp-ufs-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Vinod Koul <vkoul@kernel.org>
19 - qcom,msm8996-qmp-ufs-phy
20 - qcom,msm8998-qmp-ufs-phy
21 - qcom,sc8180x-qmp-ufs-phy
22 - qcom,sc8280xp-qmp-ufs-phy
23 - qcom,sdm845-qmp-ufs-phy
[all …]
Dqcom,qmp-pcie-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,qmp-pcie-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Vinod Koul <vkoul@kernel.org>
19 - qcom,ipq6018-qmp-pcie-phy
20 - qcom,ipq8074-qmp-gen3-pcie-phy
21 - qcom,ipq8074-qmp-pcie-phy
22 - qcom,msm8998-qmp-pcie-phy
23 - qcom,sc8180x-qmp-pcie-phy
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Dnvidia,tegra124-xusb-padctl.txt5 signals) which connect directly to pins/pads on the SoC package. Each lane
8 and thus contains any logic common to all its lanes. Each lane can be
11 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
12 super-speed USB. Other lanes are for various types of low-speed, full-speed
13 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
14 contains a software-configurable mux that sits between the I/O controller
17 In addition to per-lane configuration, USB 3.0 ports may require additional
18 settings on a per-board basis.
20 Pads will be represented as children of the top-level XUSB pad controller
21 device tree node. Each lane exposed by the pad will be represented by its
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/display/bridge/
Dti,sn65dsi83.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marek Vasut <marex@denx.de>
13 Texas Instruments SN65DSI83 1x Single-link MIPI DSI
14 to 1x Single-link LVDS
16 Texas Instruments SN65DSI84 1x Single-link MIPI DSI
17 to 1x Dual-link or 2x Single-link LVDS
23 - ti,sn65dsi83
24 - ti,sn65dsi84
[all …]
Dtoshiba,tc358775.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Vinay Simha BN <simhavcs@gmail.com>
15 MIPI DSI-RX Data 4-lane, CLK 1-lane with data rates up to 800 Mbps/lane.
17 Up to 1600x1200 24-bit/pixel resolution for single-link LVDS display panel
19 Up to WUXGA (1920x1200 24-bit pixels) resolution for dual-link LVDS display
30 vdd-supply:
33 vddio-supply:
36 stby-gpios:
[all …]
Dps8640.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nicolas Boichat <drinkcat@chromium.org>
13 The PS8640 is a low power MIPI-to-eDP video format converter supporting
15 device accepts a single channel of MIPI DSI v1.1, with up to four lanes
16 plus clock, at a transmission rate up to 1.5Gbit/sec per lane. The
18 3.24Gbit/sec per lane.
28 powerdown-gpios:
32 reset-gpios:
[all …]
/Linux-v6.1/drivers/edac/
Dthunderx_edac.c8 * Copyright Cavium, Inc. (C) 2015-2017. All rights reserved.
56 while (descr->type && descr->mask && descr->descr) { in decode_register()
57 if (reg & descr->mask) { in decode_register()
59 descr->type == ERR_CORRECTED ? in decode_register()
61 descr->descr); in decode_register()
63 size -= ret; in decode_register()
71 return (data >> pos) & ((1 << width) - 1); in get_bits()
127 .descr = "Single-bit ECC error",
137 .descr = "Double-bit ECC error",
142 .descr = "Non-existent memory write",
[all …]
/Linux-v6.1/drivers/gpu/drm/bridge/
Dtc358775.c1 // SPDX-License-Identifier: GPL-2.0
16 #include <linux/media-bus-format.h>
36 /* DSI D-PHY Layer Registers */
37 #define D0W_DPHYCONTTX 0x0004 /* Data Lane 0 DPHY Tx Control */
38 #define CLW_DPHYCONTRX 0x0020 /* Clock Lane DPHY Rx Control */
39 #define D0W_DPHYCONTRX 0x0024 /* Data Lane 0 DPHY Rx Control */
40 #define D1W_DPHYCONTRX 0x0028 /* Data Lane 1 DPHY Rx Control */
41 #define D2W_DPHYCONTRX 0x002C /* Data Lane 2 DPHY Rx Control */
42 #define D3W_DPHYCONTRX 0x0030 /* Data Lane 3 DPHY Rx Control */
44 #define CLW_CNTRL 0x0040 /* Clock Lane Control */
[all …]
/Linux-v6.1/drivers/gpu/drm/gma500/
Dcdv_intel_dp.c44 * struct i2c_algo_dp_aux_data - driver interface structure for i2c over dp
49 * @aux_ch: driver callback to transfer a single byte of the i2c payload
59 /* Run a single AUX_CH I2C transaction, writing/reading data as necessary */
64 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data; in i2c_algo_dp_aux_transaction()
67 ret = (*algo_data->aux_ch)(adapter, mode, in i2c_algo_dp_aux_transaction()
84 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data; in i2c_algo_dp_aux_address()
91 algo_data->address = address; in i2c_algo_dp_aux_address()
92 algo_data->running = true; in i2c_algo_dp_aux_address()
103 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data; in i2c_algo_dp_aux_stop()
110 if (algo_data->running) { in i2c_algo_dp_aux_stop()
[all …]
/Linux-v6.1/drivers/phy/tegra/
Dxusb.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014-2022, NVIDIA CORPORATION. All rights reserved.
31 if (args->args_count != 0) in tegra_xusb_pad_of_xlate()
32 return ERR_PTR(-EINVAL); in tegra_xusb_pad_of_xlate()
34 for (i = 0; i < pad->soc->num_lanes; i++) { in tegra_xusb_pad_of_xlate()
35 if (!pad->lanes[i]) in tegra_xusb_pad_of_xlate()
38 if (pad->lanes[i]->dev.of_node == args->np) { in tegra_xusb_pad_of_xlate()
39 phy = pad->lanes[i]; in tegra_xusb_pad_of_xlate()
45 phy = ERR_PTR(-ENODEV); in tegra_xusb_pad_of_xlate()
53 .compatible = "nvidia,tegra124-xusb-padctl",
[all …]
/Linux-v6.1/drivers/phy/cadence/
Dphy-cadence-torrent.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/phy/phy-cadence.h>
12 #include <linux/clk-provider.h>
174 /* PMA TX Lane registers */
195 /* PMA RX Lane registers */
230 /* PHY PCS lane registers */
241 [CDNS_TORRENT_REFCLK_DRIVER] = "refclk-driver",
242 [CDNS_TORRENT_DERIVED_REFCLK] = "refclk-der",
243 [CDNS_TORRENT_RECEIVED_REFCLK] = "refclk-rec",
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/pinctrl/
Dnvidia,tegra124-xusb-padctl.txt7 needed for USB. For the new binding, see ../phy/nvidia,tegra-xusb-padctl.txt.
14 This document defines the device-specific binding for the XUSB pad controller.
16 Refer to pinctrl-bindings.txt in this directory for generic information about
17 pin controller device tree bindings and ../phy/phy-bindings.txt for details on
21 --------------------
22 - compatible: For Tegra124, must contain "nvidia,tegra124-xusb-padctl".
23 Otherwise, must contain '"nvidia,<chip>-xusb-padctl",
24 "nvidia-tegra124-xusb-padctl"', where <chip> is tegra132 or tegra210.
25 - reg: Physical base address and length of the controller's registers.
26 - resets: Must contain an entry for each entry in reset-names.
[all …]
/Linux-v6.1/drivers/net/ethernet/sfc/falcon/
Dtxc43128_phy.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright 2006-2011 Solarflare Communications Inc.
9 * see www.transwitch.com, part is TXC-43128
30 * Compile-time config
52 /* Lane power-down */
56 * initiates a logic reset. Self-clearing */
63 /* Lane selection */
69 /* Lane power-down */
79 /* Bit position of value for lane 0 (or 2) */
81 /* Bit position of value for lane 1 (or 3) */
[all …]
/Linux-v6.1/drivers/gpu/drm/i915/display/
Dintel_dpio_phy.c2 * Copyright © 2014-2016 Intel Corporation
42 * IOSF-SB port.
45 * houses a common lane part which contains the PLL and other common
46 * logic. CH0 common lane also contains the IOSF-SB logic for the
56 * each spline is made up of one Physical Access Coding Sub-Layer
61 * Additionally the PHY also contains an AUX lane with AUX blocks
67 * Generally on VLV/CHV the common lane corresponds to the pipe and
83 * For single channel PHY (CHV):
100 * ---------------------------------
103 * |---------------|---------------| Display PHY
[all …]
/Linux-v6.1/drivers/phy/
Dphy-xgene.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * AppliedMicro X-Gene Multi-purpose PHY driver
10 * The APM X-Gene PHY consists of two PLL clock macro's (CMU) and lanes.
19 * -----------------
20 * | Internal | |------|
21 * | Ref PLL CMU |----| | ------------- ---------
22 * ------------ ---- | MUX |-----|PHY PLL CMU|----| Serdes|
23 * | | | | ---------
24 * External Clock ------| | -------------
25 * |------|
[all …]
/Linux-v6.1/Documentation/driver-api/nvdimm/
Dbtt.rst2 BTT - Block Translation Table
14 using stored energy in capacitors to complete in-flight block writes, or perhaps
15 in firmware. We don't have this luxury with persistent memory - if a write is in
23 the heart of it, is an indirection table that re-maps all the blocks on the
37 next arena). The following depicts the "On-disk" metadata layout::
40 Backing Store +-------> Arena
41 +---------------+ | +------------------+
43 | Arena 0 +---+ | 4K |
44 | 512G | +------------------+
46 +---------------+ | |
[all …]
/Linux-v6.1/drivers/gpu/drm/bridge/analogix/
Danalogix_dp_core.c1 // SPDX-License-Identifier: GPL-2.0-or-later
83 * "force-hpd" would indicate whether driver need this. in analogix_dp_detect_hpd()
85 if (!dp->force_hpd) in analogix_dp_detect_hpd()
86 return -ETIMEDOUT; in analogix_dp_detect_hpd()
93 dev_dbg(dp->dev, "failed to get hpd plug status, try to force hpd\n"); in analogix_dp_detect_hpd()
98 dev_err(dp->dev, "failed to get hpd plug in status\n"); in analogix_dp_detect_hpd()
99 return -EINVAL; in analogix_dp_detect_hpd()
102 dev_dbg(dp->dev, "success to get plug in status after force hpd\n"); in analogix_dp_detect_hpd()
112 ret = drm_dp_dpcd_readb(&dp->aux, DP_PSR_SUPPORT, &psr_version); in analogix_dp_detect_sink_psr()
114 dev_err(dp->dev, "failed to get PSR version, disable it\n"); in analogix_dp_detect_sink_psr()
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/pci/
Drockchip-pcie-host.txt4 - #address-cells: Address representation for root ports, set to <3>
5 - #size-cells: Size representation for root ports, set to <2>
6 - #interrupt-cells: specifies the number of cells needed to encode an
8 - compatible: Should contain "rockchip,rk3399-pcie"
9 - reg: Two register ranges as listed in the reg-names property
10 - reg-names: Must include the following names
11 - "axi-base"
12 - "apb-base"
13 - clocks: Must contain an entry for each entry in clock-names.
14 See ../clocks/clock-bindings.txt for details.
[all …]
/Linux-v6.1/drivers/net/pcs/
Dpcs-lynx.c1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
8 #include <linux/pcs-lynx.h>
38 #define lynx_to_phylink_pcs(lynx) (&(lynx)->pcs)
44 return lynx->mdio; in lynx_get_mdio_device()
51 struct mii_bus *bus = pcs->bus; in lynx_pcs_get_state_usxgmii()
52 int addr = pcs->addr; in lynx_pcs_get_state_usxgmii()
59 state->link = !!(status & MDIO_STAT1_LSTATUS); in lynx_pcs_get_state_usxgmii()
60 state->an_complete = !!(status & MDIO_AN_STAT1_COMPLETE); in lynx_pcs_get_state_usxgmii()
61 if (!state->link || !state->an_complete) in lynx_pcs_get_state_usxgmii()
79 state->link = false; in lynx_pcs_get_state_2500basex()
[all …]
/Linux-v6.1/drivers/nvdimm/
Dbtt.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright (c) 2014-2015, Intel Corporation.
18 #include <linux/backing-dev.h>
29 return &arena->nd_btt->dev; in to_dev()
34 return offset + nd_btt->initial_offset; in adjust_initial_offset()
40 struct nd_btt *nd_btt = arena->nd_btt; in arena_read_bytes()
41 struct nd_namespace_common *ndns = nd_btt->ndns; in arena_read_bytes()
51 struct nd_btt *nd_btt = arena->nd_btt; in arena_write_bytes()
52 struct nd_namespace_common *ndns = nd_btt->ndns; in arena_write_bytes()
68 dev_WARN_ONCE(to_dev(arena), !IS_ALIGNED(arena->infooff, 512), in btt_info_write()
[all …]
/Linux-v6.1/drivers/net/dsa/mv88e6xxx/
Dchip.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Marvell 88E6xxx Ethernet switch single-chip definition
28 /* PVT limits for 4-bit port and 5-bit switch */
107 * enum mv88e6xxx_edsa_support - Ethertype DSA tag support level
146 * ports 2-4 are not routet to pins.
149 /* Multi-chip Addressing Mode.
151 * when it is non-zero, and use indirect access to internal registers.
154 /* Dual-chip Addressing Mode
332 /* Handles automatic disabling and re-enabling of the PHY
402 /* Per-port timestamping resources. */
[all …]

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