Searched +full:sierra +full:- +full:phy +full:- +full:t0 (Results 1 – 4 of 4) sorted by relevance
1 Cadence Sierra PHY2 -----------------------5 - compatible: Must be "cdns,sierra-phy-t0" for Sierra in Cadence platform6 Must be "ti,sierra-phy-t0" for Sierra in TI's J721E SoC.7 - resets: Must contain an entry for each in reset-names.9 - reset-names: Must include "sierra_reset" and "sierra_apb".10 "sierra_reset" must control the reset line to the PHY.11 "sierra_apb" must control the reset line to the APB PHY13 - reg: register range for the PHY.14 - #address-cells: Must be 1[all …]
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2 # Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/4 ---5 $id: "http://devicetree.org/schemas/phy/ti,phy-j721e-wiz.yaml#"6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"11 - Kishon Vijay Abraham I <kishon@ti.com>16 - ti,j721e-wiz-16g17 - ti,j721e-wiz-10g19 power-domains:24 description: clock-specifier to represent input to the WIZ[all …]
1 // SPDX-License-Identifier: GPL-2.03 * Cadence Sierra PHY Driver14 #include <linux/phy/phy.h>22 #include <dt-bindings/phy/phy.h>24 /* PHY register offsets */155 struct phy *phy; member211 u32 offset = reg << ctx->reg_offset_shift; in cdns_regmap_write()213 writew(val, ctx->base + offset); in cdns_regmap_write()221 u32 offset = reg << ctx->reg_offset_shift; in cdns_regmap_read()223 *val = readw(ctx->base + offset); in cdns_regmap_read()[all …]
1 // SPDX-License-Identifier: GPL-2.05 * Copyright (C) 2016-2019 Texas Instruments Incorporated - https://www.ti.com/7 #include <dt-bindings/phy/phy.h>8 #include <dt-bindings/mux/mux.h>9 #include <dt-bindings/mux/ti-serdes.h>13 compatible = "mmio-sram";15 #address-cells = <1>;16 #size-cells = <1>;19 atf-sram@0 {24 scm_conf: scm-conf@100000 {[all …]
